EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 247

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
LVDS SERDES and DPA Block Diagram
LVDS SERDES and DPA Block Diagram
Figure 8–3. LVDS SERDES and DPA Block Diagram
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two PLLs
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
on the right side of the device are required.
Figure
rx_divfwdclk
rx_outclock
tx_coreclock
8–3:
Fabric
FPGA
rx_out
tx_in 10
10
The Arria II GX devices have dedicated SERDES and DPA circuitry for LVDS
transmitters and receivers on the right side. The Arria II GZ devices have dedicated
SERDES and DPA circuitry for LVDS transmitters and receivers on the row I/O banks.
Figure 8–3
interface signals for the transmitter and receiver datapaths. For more information,
refer to
page
8–11.
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
“Differential Transmitter” on page 8–8
2
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
shows the LVDS SERDES and DPA block diagram. This diagram shows the
tx_coreclock)
DIN
IOE
2
2
PLL (4)
Clock Multiplexer
3
DOUT
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
(Note
diffioclk
DIN
1), (2),
rx_inclock/tx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DOUT
(3)
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
and
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
“Differential Receiver” on
DPA Clock
DPA Circuitry
Data
LVDS Transmitter
DIN
LVDS Receiver
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
rx_in
tx_out
8–7