EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 473

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Test Modes
Figure 1–83. Reverse Serial Pre-CDR Loopback Datapath
Note to
(1) The only active block of the transmitter channel is the transmitter buffer.
December 2010 Altera Corporation
Fabric
FPGA
Figure
Reverse Serial Pre-CDR Loopback
1–83:
Reverse serial pre-CDR loopback is available in Basic functional mode only. In this
mode, the data received through the rx_datain port is looped back to the tx_dataout
port before the receiver CDR. The received data is also available to the FPGA logic.
You can enable the reverse serial pre-CDR loopback option using the ALTGX
MegaWizard Plug-In Manager. Unlike other loopback modes, there is no dynamic pin
control to enable or disable reverse serial pre-CDR loopback.
Figure 1–83
loopback mode.
You can change the V
Plug-In Manager. However, you cannot change the pre-emphasis settings for the
transmitter buffer.
tx_clkout[0]
Compensation
wrclk
shows the transceiver channel datapath for reverse serial pre-CDR
TX Phase
FIFO
rdclk
OD
on the transmitter buffer through the ALTGX MegaWizard
/2
wrclk
Byte Serializer
/2
Receiver Channel PCS
(Note 1)
Transmitter Channel PCS
rdclk
8B/10B Encoder
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Parallel Recovery Clock
High-Speed
Serial Clock
Transmitter Channel
Receiver Channel
PMA
Pre-CDR Loopback
Reverse Serial
PMA
1–87