EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 564
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–6
Arria II Device Handbook Volume 2: Transceivers
Multiple Channels Sharing Two CMU PLLs
1
In some cases, a single CMU PLL is not sufficient to run the transmitter channels
within a transceiver block at the desired data rates.
Use a second CMU PLL if you want to combine channels that require different
configurations, such as:
■
■
■
Example 2
Consider a design that requires four channels set up in a Receiver and Transmitter
configuration in the same transceiver block at the serial data rates shown in
Table 3–2. Configuration for Example 2 for Arria II Devices
Assume that instance 0, 1, and 2 are driven from the same clock source and have the
same CMU PLL bandwidth settings. In this case, you can use one CMU PLL for
instance 0, 1, and 2. For the ALTGX MegaWizard Plug-In Manager settings that enable
the Quartus II software to share the same CMU PLL, refer to
page
You can force the placement of transceiver channels to a specific transceiver block by
assigning pins to the tx_dataout and rx_datain pins of the four ALTGX instances.
Otherwise, the Quartus II software selects a transceiver block.
Figure 3–2
software combines the transceiver channels within the same transceiver block.
Because the RX CDR is not shared between channels, only the CMU PLLs are shown.
You must connect the pll_powerdown port of instance 0, 1, and 2 to the same logic
output to share the same CMU PLL for these instances.
inst0
inst1
inst2
inst3
Instance Name
User-Created
Quartus II software-defined protocols (for example, Basic, Gbps Ethernet (GbE),
SONET/synchronous digital hierarchy [SDH], Serial Digital Interface [SDI], or PCI
Express
CMU PLL bandwidth settings
Different input reference clocks
3–3. A second CMU PLL is required for instance 3.
shows the transceiver configuration before and after the Quartus II
®
[PIPE] [PCIe] modes)
Number of Channels
1
1
1
1
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
ALTGX MegaWizard Plug-In Manager Settings
Receiver and Transmitter
Receiver and Transmitter
Receiver and Transmitter
Receiver and Transmitter
Configuration
December 2010 Altera Corporation
“Example 1” on
Effective Data Rate
0.9375
(Gbps)
1.875
Sharing CMU PLLs
3.75
2
Table
3–2.
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