EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 520

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–30
Table 2–9. FPGA Fabric-Transceiver Interface Clocks for Arria II Devices (Part 2 of 2)
Arria II Device Handbook Volume 2: Transceivers
Note to
(1) For more information about global, regional, and periphery clock resources available in each device, refer to the
coreclkout
Clock Name
rx_clkout
fixed_clk
Arria II Devices
Table
FPGA Fabric-Transmitter Interface Clocking
2–9:
1
chapter.
“FPGA Fabric-Transmitter Interface Clocking”
Clocking” on page 2–42
and receiver phase compensation FIFO clocks in order to reduce the global, regional,
and periphery clock resource utilization in your design.
The transmitter phase compensation FIFO compensates for the phase difference
between the FPGA fabric clock (phase compensation FIFO write clock) and the
parallel transmitter PCS clock (phase compensation FIFO read clock). The transmitter
phase compensation FIFO write clock forms the FPGA fabric-transmitter interface
clock. The phase compensation FIFO write and read clocks must have exactly the
same frequency, in other words, 0 parts per million (PPM) frequency difference.
Arria II GX and GZ transceivers provide the following two options for selecting the
transmitter phase compensation FIFO write clock:
■
■
Quartus II Software-Selected Transmitter Phase Compensation FIFO Write
Clock
If you do not select the tx_coreclk port in the ALTGX MegaWizard
Manager, the Quartus II software automatically selects the transmitter phase
compensation FIFO write clock for each channel in that ALTGX instance. The
Quartus II software selects the FIFO write clock depending on the channel
configuration.
Non-Bonded Channel Configuration
In the non-bonded channel configuration, the transmitter channels may or may not be
identical. Identical transmitter channels are defined as channels that have exactly the
same CMU PLL input reference clock source, have exactly the same CMU PLL
configuration, and have exactly the same transmitter PMA and PCS configuration.
Identical transmitter channels may have different transmitter voltage output
differential (VOD) or pre-emphasis settings.
Phase compensation FIFO clock
Phase compensation FIFO clock
Quartus II software-selected transmitter phase compensation FIFO write clock
User-selected transmitter phase compensation FIFO write clock
PCIe receiver detect clock
Clock Description
describe the criteria and methodology to share transmitter
Transceiver-to-FPGA fabric
Transceiver-to-FPGA fabric
FPGA fabric-to-transceiver
Interface Direction
and
Chapter 2: Transceiver Clocking in Arria II Devices
“FPGA Fabric-Receiver Interface
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
Resource Utilization
Global, Regional clocks
Clock Networks and PLLs in
FPGA Fabric Clock
Global, Regional,
Global, Regional,
Periphery clocks
Periphery clocks
™
Plug-In
(1)