EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 199
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–2. External Memory Interface Datapath Overview for Arria II GZ Devices
Notes to
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Arria II GZ IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
Memory Interfaces Pin Support for Arria II Devices
December 2010 Altera Corporation
Arria II GZ FPGA
and write operations.
Management
and Reset
Figure
Clock
7–2:
f
1
Half-Rate Resynchronization Clock
DQ Write Clock
Half-Rate Clock
DQS Write Clock
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM or BWSn) pins to enable write masking. This section describes how Arria II
devices support all these pins.
If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
For more information about pin connections, refer to the
Connection
The DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use CK and CK# signals to
capture the address and command signals. You can generate these signals to mimic
the write-data strobe with Arria II DDR I/O registers (DDIOs) to ensure that timing
relationships between the CK/CK# and DQS signals (t
DDR2, and DDR SDRAM devices) are met. The QDR II+/QDR II SRAM devices use
the same clock (K/K#) to capture the write data, address, and command signals.
DPRAM
Guidelines.
4n
4n
4
Postamble Enable
Postamble Clock
Half Data Rate
Input Registers
Output Registers
Output Registers
Half Data Rate
Half Data Rate
2n
Resynchronization Clock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Synchronization
Postamble
Registers
Control
DLL
Circuit
2n
2
2n
DDR Input
(Note
DQS Enable
Registers
DQS Logic
DDR Output
DDR Output
and Output
and Output
Registers
Registers
Enable
Enable
Circuit
Block
DQSS
Arria II Device Family Pin
1),
, t
(2)
DSS
, and t
n
n
DSH
DQS (Read) (3)
DQ (Read) (3)
DQ (Write) (3)
DQS (Write) (3)
Memory
in DDR3,
7–3
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