EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 40
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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2–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in
arithmetic or shared arithmetic mode. The two-bit carry select feature in Arria II
devices halves the propagation delay of carry chains within the ALM. Carry chains
can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during design
processing, or you can create it manually during design entry. Parameterized
functions such as LPM automatically take advantage of carry chains for the
appropriate functions.
The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. To
enhance fitting, a long carry chain runs vertically, allowing fast horizontal connections
to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full
column.
To avoid routing congestion in one small area of the device when a high fan-in
arithmetic function is implemented, the LAB can support carry chains that only use
either the top half or bottom half of the LAB before connecting to the next LAB. This
leaves the other half of the ALMs in the LAB available for implementing narrower
fan-in functions in normal mode. Carry chains that use the top five ALMs in the first
LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains
that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs
in the next LAB within the column. In every alternate LAB column, the top half can be
bypassed; in the other MLAB columns, the bottom half can be bypassed.
For more information on carry chain interconnect, refer to
page
2–17.
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
“ALM Interconnects” on
December 2010 Altera Corporation
Adaptive Logic Modules
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