EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 67
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
Figure 3–19. Read-During-Write Data Flow
Figure 3–20. MLABs Blocks Same Port Read-During Write: Don’t Care Mode
December 2010 Altera Corporation
Read-During-Write Behavior
q(unregistered)
q(registered)
address
data_in
wrena
clk_a
You can customize the read-during-write behavior of the Arria II memory blocks to
suit your design requirements. The two types of read-during-write operations are
same port and mixed port.
and mixed port.
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true dual-port
RAM. In same-port read-during-write mode, three output choices are available: new
data mode (or flow-through), old data mode, or don’t care mode. In new data mode,
the new data is available on the rising edge of the same clock cycle on which it was
written. In old data mode, the RAM outputs reflect the old data at that address before
the write operation proceeds. In don’t care mode, the RAM outputs “don’t care”
values for a read-during-write operation.
Figure 3–20
behavior in don’t care mode for MLABs.
XX
XX
XX
Port A
data in
Port A
data out
XX
A0(old data)
shows sample functional waveforms of same-port read-during-write
FFFF
A0
FFFF
Figure 3–19
FFFF
Arria II Device Handbook Volume 1: Device Interfaces and Integration
A1(old data)
shows the difference between the same port
Port B
data in
Port B
data out
AAAA
A1
AAAA
AAAA
Mixed-port
data flow
Same-port
data flow
A2(old data)
XXXX
A2
3–21
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