EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 228
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–32
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Phase Offset Control
f
There are seven different frequency modes for Arria II GX DLLs, and eight different
frequency modes for Arria II GZ DLLs as shown in
provides different phase-shift selections. In frequency mode 0, 1, 2, and 3, the 6-bit
DQS delay settings vary with PVT to implement the phase-shift delay. In frequency
modes 4, 5, 6, and 7 only 5 bits of the DQS delay settings vary with PVT to implement
the phase-shift delay; the MSB of the DQS delay setting is set to 0.
Table 7–10. DLL Frequency Modes for Arria II Devices
For the frequency range of each mode, refer to the
For a 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when the 0°
shift is implemented. You can feed the DQS delay settings to the DQS logic block and
the logic array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you do not
use the IOE resynchronization registers. The shifted CQn signal can go to the
negative-edge input register in the DQ IOE or the logic array and is only used for
QDR II+/QDR II SRAM interfaces.
Each DLL has two phase offset modules and can provide two separate DQS delay
settings with independent offset; for Arria II GX devices, one offset goes clockwise
half-way around the chip and the other goes counter-clockwise half-way around the
chip and for Arria II GZ devices, one for the top and bottom I/O bank and one for the
left and right I/O bank. Even though you have independent phase offset control, the
frequency of the interface with the same DLL must be the same. Use the phase offset
control module for making small shifts to the input signal and use the DQS
phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a
multiple of 30° phase shift, but your interface must have a 67.5° phase shift on the
DQS signal, you can use two delay chains in the DQS logic blocks to give you a 60°
phase shift and use the phase offset control feature to implement the extra 7.5° phase
shift.
Note to
(1) Frequency mode 7 is only available for Arria II GZ devices only.
Frequency Mode
Table
7
7–10:
0
1
2
3
4
5
6
(1)
Available Phase Shift
22.5, 45, 67.5, 90
60, 120, 180, 240
36, 72, 108, 144
45, 90, 135, 180
36, 72, 108, 144
45, 90, 135, 180
30, 60, 90, 120
30, 60, 90, 120
Chapter 7: External Memory Interfaces in Arria II Devices
Device Datasheet for Arria II
Table
Arria II External Memory Interface Features
7–10. Each frequency mode
December 2010 Altera Corporation
Number of Delay Chains
16
12
10
12
10
8
8
6
Devices.
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