EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 353

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: SEU Mitigation in Arria II Devices
User Mode Error Detection
December 2010 Altera Corporation
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1
1
For more information about the timing requirement to shift out error information
from the EMR, refer to
The error detection circuitry continues to calculate the CRC_ERROR and 16-bit
signatures for the next frame of data regardless of whether an error has occurred in
the current frame or not. You must monitor the CRC_ERROR signal and take the
appropriate actions if a CRC error occurs.
The error detection circuitry in Arria II devices uses a 16-bit CRC-ANSI standard
(16-bit polynomial) as the CRC generator. The computed 16-bit CRC signature for
each frame is stored in the configuration RAM. The total storage size is 16 (number of
bits per frame) × the number of frames.
The Arria II device error detection CRC feature does not check memory blocks and
I/O buffers. Thus, the CRC_ERROR signal might stay solid high or low, depending on
the error status of the previously checked configuration RAM frame. The I/O buffers
are not verified during error detection because these bits use flipflops as storage
elements that are more resistant to soft errors when compared with configuration
RAM cells. MLAB and M9K memory blocks support parity bits that are used to check
the contents of memory blocks for any error in Arria II GX devices. In addition to
MLAB and M9K memory blocks, M144K memory blocks are used to check the
contents of memory blocks for any error in Arria II GZ devices.
For more information about error detection in Arria II memory blocks, refer to the
Memory Blocks in Arria II Devices
To provide testing capability of the error detection block, a JTAG instruction,
EDERROR_INJECT, is provided. This instruction is able to change the content of the
21-bit JTAG fault injection register used for error injection in Arria II devices, thereby
enabling the testing of the error detection block.
You can only execute the EDERROR_INJECT JTAG instruction when the device is in user
mode.
Table 10–1
Table 10–1. EDERROR_INJECT JTAG Instruction for Arria II Devices
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system and on-the-fly, without
having to reconfigure the device.
For more information about .jam, refer to
and Recovery using CRC in Altera FPGA
EDERROR_INJECT
JTAG Instruction
lists the EDERROR_INJECT JTAG instruction for Arria II devices.
“Error Detection Timing” on page
Instruction Code
00 0001 0101
chapter.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Devices.
AN 539: Test Methodology of Error Detection
This instruction controls the 21-bit JTAG fault
injection register used for error injection.
10–7.
Description
10–3