EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 513
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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- Download datasheet (22Mb)
Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–15. Receiver Datapath Clocking in ×4 Bonded Channel Configuration with Deskew FIFO
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
coreclkout
×4 Bonded Channel Configuration with Deskew FIFO
XAUI functional mode has ×4 bonded channel configuration with deskew FIFO.
Figure 2–15
with deskew FIFO.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
Channel 3
Channel 2
Channel 1
Channel 0
shows receiver datapath clocking in ×4 channel bonding configurations
Input Reference Clock
Input Reference Clock
/2
/2
/2
/2
/2
CMU1_PLL
CMU0_PLL
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
CMU1 Clock Divider
CMU0 Clock Divider
Arria II Device Handbook Volume 2: Transceivers
CMU1_Channel
CMU0_Channel
Ch3
Ch2
Ch1
Low-Speed Parallel Clock from CMU0 Clock Divider
FPGA Fabric-Transceiver Interface Clock
Serial Recovered Clock
Ch0 Parallel Recovered Clock
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
Clock
Clock
Clock
Clock
Input
Input
Input
Input
2–23
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