EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 399
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
December 2010 Altera Corporation
f
Figure 1–12
Figure 1–12. TX Phase Compensation FIFO
Notes to
(1) The tx_phase_comp_fifo_error is optional and available in all functional modes. This signal is asserted high to
(2) Use this optional clock for the FIFO write clock if you instantiate the tx_coreclk port in the ALTGX MegaWizard
(3) The tx_clkout low-speed parallel clock is from the local clock divider from the associated transmitter channel and
(4) The coreclkout clock is from the CMU0 block of the associated transceiver block or the master transceiver block for
For more information about TX phase compensation FIFO clocking, refer to the
“Limitation of the Quartus II Software-Selected Transmitter Phase Compensation
FIFO Write (or Read) Clocks” section in the
chapter.
An optional tx_phase_comp_fifo_error port is available in all functional modes and
is asserted high in an overflow or underflow condition. If this signal is asserted,
ensure that there is 0 PPM difference between the TX phase compensation FIFO read
and write clocks.
The output of this block can go to any of the following blocks:
■
■
■
Byte serializer—If you enable this block.
8B/10B encoder—If you disable the byte serializer, but enable the 8B/10B encoder
and your channel width is either 8 or 16 bits.
Serializer—If you disable both the byte serializer and the 8B/10B encoder, or if
you use low-latency PCS bypass mode.
indicate an overflow or underflow condition.
Plug-In Manager, regardless of the channel configurations. Otherwise, the same clock used for the read clock is also
used for the write clock. Ensure that there is 0 parts per million (PPM) frequency difference between the tx_coreclk
clock and the read clock of the FIFO.
is used in non-bonded configurations.
×4 bonded or ×8 bonded channel configurations, respectively.
Figure
shows the datapath and clocking of the TX phase compensation FIFO.
1–12:
tx_coreclk (2)
Interface (tx_datain)
Data Input from
Fabric of PIPE
the FPGA
wr_clk
Compensation
TX Phase
FIFO
rd_clk
Transceiver Clocking in Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Encoder or Serializer
tx_phase_comp_fifo_error (1)
the Byte Serializer
Data Output to
or the 8B/10B
tx_clkout (3)
coreclkout (4)
1–13
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