EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 583

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–5. Sample Reset Sequence of Four Receiver and Transmitter Channels—Receiver CDR in Manual Lock Mode
Note to
(1) For the transceiver block power down duration, refer to the
December 2010 Altera Corporation
Reset Signals
CDR Control Signals
Output Status Signals
Figure
rx_locktorefclk[0]
rx_locktorefclk[3]
4–5:
rx_locktodata[0]
rx_locktodata[3]
pll_powerdown
rx_analogreset
rx_pll_locked[0]
rx_pll_locked[3]
rx_digitalreset
tx_digitalreset
pll_locked
busy
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in manual lock mode, use the reset sequence
shown in
1
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 7).
have gone high, from that point onwards, wait for at least 4 s for the receiver
parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8).
At this point, all the receivers are ready for data traffic.
1 μs (1)
Figure
2
4–5.
3
Two parallel clock cycles
4
Device Datasheet for Arria II Devices
5
6
7
7
15 μs (1)
8
8
8
8
4 μs (1)
Arria II Device Handbook Volume 2: Transceivers
chapter in the Arria II Device Handbook.
9
4–9