CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 97

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller
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AMD Geode™ CS5535 Companion Device Data Book
Software loads the starting address of the PRD table
by programming the PRD Table Address register.
Example - Program the PRD Table Address register
with Address_3.
Software must fill the buffers pointed to by the PRDs
with audio data. It is not absolutely necessary to fill the
buffers; however, the buffer filling process must stay
ahead of the buffer emptying. The simplest way to do
this is by using the EOP flags to generate an interrupt
when an audio buffer is empty.
Example - Fill Audio Buffer_1 and Audio Buffer_2.
Ensure than an interrupt service routine is assigned to
the audio interrupt.
Read the IRQ Status register to clear the Bus Master
Error and End of Page flags (if set).
Program the AC97 codec properly to receive audio
data (mixer settings, etc.).
Engage the bus master by setting the Bus Master
Enable bit.
The bus master reads the PRD entry pointed to by the
PRD Table Address register. Using the address from
the PRD, it begins the audio transfer. The PRD Table
Address register is incremented by eight.
Example - The bus master is now properly pro-
grammed to transfer Audio Buffer_1 to a specific
slot(s) in the AC97 interface.
The bus master transfers data from memory and
sends it to the AC97 Codec. At the completion of each
PRD, the bus master’s next response depends on the
settings of the flags in the PRD.
Example - After transferring the data described by
PRD_1, an interrupt is generated because the EOP bit
is set, and the bus master continues on to PRD_2. The
interrupt service routine reads the Second Level Audio
IRQ Status register to determine which bus master to
service. It refills Audio Buffer_1 and then reads the
bus master’s IRQ Status register to clear the End of
Page flag and the interrupt.
After transferring the data described by PRD_2,
another interrupt is generated because the EOP bit is
set, and the bus master continues on to PRD_3. The
interrupt service routine reads the Second Level Audio
IRQ Status register to determine which bus master to
service. It refills Audio Buffer_2 and then reads the
bus master’s IRQ Status register to clear the End of
Page flag and the interrupt.
PRD_3 has the JMP bit set. This means the bus mas-
ter uses the address stored in PRD_3 (Address_3) to
locate the next PRD. It does not use the address in the
PRD Table Address register to get the next PRD.
Since Address_3 is the location of PRD_1, the bus
master has looped the PRD table. No interrupt is gen-
erated for PRD_3.
Codec Register Access
The ACC provides a set of registers that serve as an inter-
face to the AC97 codec’s registers. The Codec Command
register allows software to initiate a read or a write of a
codec register. The Codec Status register allows software
to read back the data from the codec after a read operation
has completed. Since the AC Link runs very slow relative to
core CPU speed (and therefore software speed), it is nec-
essary for software to wait between issuing commands to
the codec.
For register reads, software specifies a command address
and sets both the read/write flag and the Codec Command
New flag in the Codec Control register. Software must then
wait for the Codec Status New bit to be set before using the
returned status data in the Codec Status register. Before
issuing another read command, software must wait for the
Codec Command New flag to be cleared by hardware.
(Note: Codec Command New will clear before Codec Sta-
tus New is set; therefore, a second read can be issued
before the result of the current read is returned).
For register writes, software specifies a command address
and command data using the Codec Control register. At
the same time it must set the Codec Command New flag.
Before issuing another read or write, software must wait for
the Codec Command New flag to clear. See Section 6.3
"AC97 Audio Codec Controller Register Descriptions" for
details on the Codec register interface.
Pausing the bus master can be accomplished by set-
ting the Bus Master Pause bit in its control register.
The bus master stops immediately on the current sam-
ple being processed. Upon resuming, the bus master
(clearing the Bus Master Pause bit), resumes on the
exact sample where it left off.
The bus master can be stopped in the middle of a
transfer by clearing the Bus Master Enable bit in its
control register. In this case, the bus master will not
remember what sample it left off on. If it is re-enabled,
it will begin by reading the PRD entry pointed to by its
PRD Table Address register. If software does not re-
initialize this pointer, it will be pointing to the PRD entry
immediately following the PRD entry that was being
processed. This may be an invalid condition if the bus
master was disabled while processing the last PRD in
a PRD table (PRD Table Address register pointing to
memory beyond the table).
Note that if the Bus Master Error bit is set, the interrupt
service routine should refill two buffers instead of one,
because a previous interrupt was missed (unless it
was intentionally missed). For this to work correctly,
the service routine should read the Second Level
Audio IRQ Status register, fill the buffer of the bus
master needing service, read the bus master’s IRQ
Status register, and then fill the next buffer if the Bus
Master Error bit was set. Failing to fill the first buffer
before reading the IRQ Status register would possibly
resume the bus master too early and result in sound
being played twice or data being overwritten (if record-
ing).
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