CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 185

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Flash Controller
5.18.1.3 NAND ECC Control Module
The NAND ECC Control Module is part of the NAND Flash
Controller. It calculates 22-bit ECC parity for each of the
256 bytes of the NAND Flash’s data transferred on the
Local bus. The ECC calculation algorithm follows the
SmartMedia Physical Format Specification. The ECC algo-
rithm is capable of single-bit correction and 2-bit random-
error detection. ECCs are generated only for data areas
and no ECC is generated for page-data redundant areas
containing ECCs as the page-data redundant area is dupli-
cated for reliability. For ECC calculations, 256 bytes are
handled as a stream of 2048-bit serial data. In the event of
an error, the error-correction feature can detect the bit
location of the error based on the results of a parity check
and correct the data.
Hardware Operation
The ECC engine treats 256-byte data as a block. Each
byte has an 8-bit address called a Line Address (LA). Each
bit in a byte has a 3-bit address called a Column Address
(CA). Combining these two address fields forms an 11-bit
unique address for every single bit in the 256-byte data
block. The address uses the notation: LLLL_LLLL, CCC.
This module contains an 8-bit counter to keep track of the
LA of each byte. Each ECC parity bit calculation in the
ECC engine produces even parity of half of the data bits in
the block. Different parity bits use different sets of the bits.
For example, CP0 is the even parity bit of the bits with Col-
umn Address bit 0 equals 0. CP1 is the even parity bit of
the bits with Column Address bit 0 equals 1. Both odd and
even parity are supported for ECC. The ECC parity avail-
able in the NAND ECC column, LSB line, and MSB line
parity registers is the inverted output of the ECC parity from
the ECC engine in the case of odd ECC parity and the non-
inverted output in the case of even parity. Table 5-36 lists
the relationship between the parity bits and the corre-
sponding bit addresses. The hardware ECC engine calcu-
lates 22-bit ECC parity whenever there is a data write or
data read to/from the NAND Flash device. On power-up,
the ECC engine is configured to be odd parity. Even or odd
ECC parity is controlled by bit 2 of NAND ECC Control reg-
ister (Flash Memory Offset 815h).
AMD Geode™ CS5535 Companion Device Data Book
Table 5-36. ECC Parity/Bit Address Relationship
Parity
LP00
LP01
LP02
LP03
LP04
LP05
LP06
LP07
LP08
LP09
LP10
LP11
LP12
LP13
LP14
LP15
CP0
CP1
CP2
CP3
CP4
CP5
31506B
xxxx_xxxx, xx0
xxxx_xxxx, xx1
xxxx_xxxx, x0x
xxxx_xxxx, x1x
xxxx_xxxx, 0xx
xxxx_xxxx, 1xx
xxxx_xxx0, xxx
xxxx_xxx1, xxx
xxxx_xx0x, xxx
xxxx_xx1x, xxx
xxxx_x0xx, xxx
xxxx_x1xx, xxx
xxxx_0xxx, xxx
xxxx_1xxx, xxx
xxx0_xxxx, xxx
xxx1_xxxx, xxx
xx0x_xxxx, xxx
xx1x_xxxx, xxx
x0xx_xxxx, xxx
x1xx_xxxx, xxx
0xxx_xxxx, xxx
1xxx_xxxx, xxx
Bit Address
185