CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 226

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
6.1.4.2
IOD Swiss Cheese 0 (GLIU_IOD_SC0)
MSR Address
Type
Reset Value
IOD Swiss Cheese 1 (GLIU_IOD_SC1)
MSR Address
Type
Reset Value
IOD Swiss Cheese 2 (GLIU_IOD_SC2)
MSR Address
Type
Reset Value
IOD Swiss Cheese 3 (GLIU_IOD_SC3)
MSR Address
Type
Reset Value
Each of these eight descriptors checks that the physical address supplied by the device’s request on the address bits is
equal to the IBASE_SC field of descriptor register bits and that the enable write or read conditions given by the descriptor
register fields WEN and REN respectively matches the request type and enable fields given on the physical address bits of
the device’s request. If the above matches, then the descriptor has a hit condition and routes the received address to the
programmed destination ID, IDID1_SC field of the descriptor register bits.
226
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IDID_SC
59:40
39:20
19:0
Bit
IOD Swiss Cheese Descriptors (GLIU_IOD_SC[x])
EN_SC
Name
RSVD
IBASE_BM
IMASK_BM
510100EAh
R/W
60000000_403003F0h
510100EBh
R/W
00000000_00000000h
510100ECh
R/W
00000000_00000000h
510100EDh
R/W
00000000_00000000h
31506B
RSVD
Description
Reserved. Write as read.
Physical I/O Address Base.These bits form the matching value against which the
masked value of the physical address, bits [31:12] are directly compared. If a match is
found, then a hit is declared, depending on the setting of the BIZZARO flag comparator.
Physical I/O Address Mask. These bits are used to mask address bits [31:12] for the
purposes of this hit detection.
GLIU_IOD_BM[x] Bit Descriptions (Continued)
GLIU_IOD_SC[x] Register
IOD Swiss Cheese 4 (GLIU_IOD_SC4)
MSR Address
Type
Reset Value
IOD Swiss Cheese 5 (GLIU_IOD_SC5)
MSR Address
Type
Reset Value
IOD Swiss Cheese 6 (GLIU_IOD_SC6)
MSR Address
Type
Reset Value
IOD Swiss Cheese 7 (GLIU_IOD_SC7)
MSR Address
Type
Reset Value
RSVD
AMD Geode™ CS5535 Companion Device Data Book
IBASE_SC
GeodeLink™ Interface Unit Register Descriptions
510100EEh
R/W
00000000_00000000h
510100EFh
R/W
00000000_00000000h
510100F0h
R/W
00000000_00000000h
510100F1h
R/W
00000000_00000000h
9
8
7
6
5
4
3
2
RSVD
1
0

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