CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 445

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Real-Time Clock Register Descriptions
6.15.2.11 RTC Control Register A (RTC_CRA)
I/O Address
Type
Reset Value
This register controls test selection among other functions. This register cannot be written before reading bit 7 of
RTC_CRD (VRT bit).
AMD Geode™ CS5535 Companion Device Data Book
Bit
6:4
3:0
7
UIP
7
Name
UIP (RO)
DIV_CHN_CTL
PIR_SEL
0Ah
R/W
20h
6
DIV_CHN_CTL
Description
Update in Progress (Read Only). This RO bit is not affected by reset. This bit reads 0
when bit 7 of RTC_CRB is 1.
0: Timing registers not updated within 244 µs.
1: Timing registers updated within 244 µs.
Divider Chain Control. These R/W bits control the configuration of the divider chain for
timing generation and register bank selection. They are cleared to 010 as long as bit 7
of RTC_CRD (VRT bit) is 0.
00x: Oscillator Disabled.
010: Normal Operation.
011: Test.
Periodic Interrupt Rate Select: These R/W bits select one of fifteen output taps from
the clock divider chain to control the rate of the periodic interrupt. They are cleared to
000 as long as bit 7 of RTC_CRD (VRT bit) is 0.
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
5
No interrupts
3.906250 ms
7.812500 ms
0.122070 ms
0.244141 ms
0.488281 ms
0.976562 ms
1.953125 ms
RTC_CRA Bit Descriptions
RTC_CRA Register Map
4
3
10x: Test.
1001:
1010:
1011:
1100:
1101:
1110:
1111:
11x: Divider Chain Reset.
1000:
3.906250 ms
7.812500 ms
15.625000 ms
31.250000 ms
62.500000 ms
125.000000 ms
250.000000 ms
500.000000 ms
2
PIR_SEL
31506B
1
0
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