CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 106

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.6.1.2
This discussion applies to the following LBARs:
• MSR 51400010h: Flash Chip Select 0
• MSR 51400011h: Flash Chip Select 1
• MSR 51400012h: Flash Chip Select 2
• MSR 51400013h: Flash Chip Select 3
Note: Flash Chip Selects [3:0] can be programmed for
The I/O LBAR works just like the Fixed style, except the
size of the IO_MASK has been expanded to cover the
entire address range (see Figure 5-12). In the Fixed style,
the IO_MASK applies to bits [15:12] but for Variable style,
the IO_MASK applies to bits [15:4]. If all bits are set, then
the target size is 16 bytes and base address bits [15:4]
determine the base. Base bits [3:0] are a “don't care” and
are effectively forced to zero by the hardware. Thus, the
smallest I/O target is 16 bytes. As the LSBs of IO_MASK
are cleared, the “target space” expands. For example,
assume a 64-byte device is desired in I/O space. The
IO_MASK = FFCh, base address bits [15:6] are pro-
grammed to the desired base, and base address bits [5:4]
are cleared (see Rule on page 105).
106
Note: The memory mask is always 20 bits, which is equal to the number of memory base address bits.
(MSR_LBAR_FLSH0) with bit 34 = 0 (I/O mapped)
(MSR_LBAR_FLSH1) with bit 34 = 0 (I/O mapped)
(MSR_LBAR_FLSH2) with bit 34 = 0 (I/O mapped)
(MSR_LBAR_FLSH3) with bit 34 = 0 (I/O mapped)
ADDR[31:12]
ADDR[15:4]
I/O or a memory space. See Section 5.6.1.3 "Mem-
ory LBARs".
Variable Target Size I/O LBARs
31506B
MEM_MASK
I/O_MASK
Figure 5-12. I/O Space LBAR - Variable Target Size
Figure 5-13. Memory Space LBAR
[31:12]
[15:4]
Compare
Compare
5.6.1.3
This discussion applies to the following LBARs:
• MSR 51400009h: KEL from USB Host Controller 1
• MSR 51400010h: Flash Chip Select 0
• MSR 51400011h: Flash Chip Select 1
• MSR 51400012h: Flash Chip Select 2
• MSR 51400013h: Flash Chip Select 3
• MSR 5140000Ah: KEL from USB Host Controller 2
Note: The Flash Chip Selects [3:0] can be programmed
For memory space, the LBAR works exactly like the Vari-
able style (see Figure 5-13), except that clearing the LSBs
of the MEM_MASK begins to make sense. For example,
assume there is a 64 KB external ROM that is going to be
connected to Flash Chip Select 0. Such a device needs
address bits [15:0]. The MEM_MASK would normally be
programmed to FFFF0h and base address bits [31:16]
would be programmed to the desired base. The values in
base address [15:12] would be cleared because the asso-
ciated mask bits are cleared (see Rule on page 105).
Lastly, the memory target can not be smaller than 4 KB.
(MSR_LBAR_KEL1)
(MSR_LBAR_FLSH0) with bit 34 = 1 (memory mapped)
(MSR_LBAR_FLSH1) with bit 34 = 1 (memory mapped)
(MSR_LBAR_FLSH2) with bit 34 = 1 (memory mapped)
(MSR_LBAR_FLSH3) with bit 34 = 1 (memory mapped)
(MSR_LBAR_KEL2)
Hit
Hit
for an I/O space or a Memory space.
AMD Geode™ CS5535 Companion Device Data Book
Memory LBARs
[31:12]
[15:4]
BASE_ADDR
BASE_ADDR
Diverse Integration Logic