CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 419

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Direct Memory Access Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
I/O Address
0DCh
0D4h
0D6h
0D8h
0DAh
0DEh
08Ah
08Bh
08Fh
48Ah
48Bh
48Fh
080h
081h
082h
083h
087h
089h
481h
482h
483h
487h
489h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
Table 6-53. DMA Native Registers Summary (Continued)
Width
(Bits)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Register Name
Master DMA Channel [7:4] Channel Mask
(DMA_CH7:4_CHMSK)
Master DMA Channel [7:4] Mode
(DMA_CH7:4_MODE)
Master DMA Channel [7:4] Clear Byte Pointer
(DMA_CH7:4_CLR_PNTR)
Master DMA Channel [7:4] Master Clear
(DMA_CH7:4_MSTR_CLR)
Master DMA Channel [7:4] Clear Mask
(DMA_CH7:4_CLR_MSK)
Master DMA Channel [7:4] Write Mask
(DMA_CH7:4_WR_MSK)
Post Code Display Register (POST_DISPLAY)
DMA Channel 2 Low Page
(DMA_CH2_LO_PAGE)
DMA Channel 3 Low Page
(DMA_CH3_LO_PAGE)
DMA Channel 1 Low Page
(DMA_CH1_LO_PAGE)
DMA Channel 0 Low Page
(DMA_CH0_LO_PAGE)
DMA Channel 6 Low Page
(DMA_CH6_LO_PAGE)
DMA Channel 7 Low Page
(DMA_CH7_LO_PAGE)
DMA Channel 5 Low Page
(DMA_CH5_LO_PAGE)
DMA Channel 4 Low Page
(DMA_CH4_LO_PAGE)
DMA Channel 2 High Page
(DMA_CH2_HI_PAGE)
DMA Channel 3 High Page
(DMA_CH3_HI_PAGE)
DMA Channel 1 High Page
(DMA_CH1_HI_PAGE)
DMA Channel 0 High Page
(DMA_CH0_HI_PAGE)
DMA Channel 6 High Page
(DMA_CH6_HI_PAGE)
DMA Channel 7 High Page
(DMA_CH7_HI_PAGE)
DMA Channel 5 High Page
(DMA_CH5_HI_PAGE)
DMA Channel 4 High Page
(DMA_CH4_HI_PAGE)
31506B
Reset Value
0Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
xxh
xxh
xxh
xxh
Reference
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