CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 377

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12
The registers for the UART/IR Controller are divided into
three sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• UART/IR Controller Specific MSRs
• UART/IR Controller Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
All MSRs are 64 bits, however, the UART/IR Controller
Specific MSRs (summarized in Table 6-28) are called out
AMD Geode™ CS5535 Companion Device Data Book
Bank 0
MSR Address
DIVIL, see Section 6.6.1 on page 317.)
5140003Ch
5140003Dh
5140003Ah
5140003Bh
5140003Eh
5140003Fh
51400038h
51400039h
I/O Offset
00h
01h
02h
03h
04h
05h
UART and IR Port Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
RO
RO
RO
Table 6-29. UART/IR Controller Native Registers Summary
Table 6-28. UART/IR Controller Specific MSRs Summary
Register Name
UART1 Primary Dongle and Modem Interface
(UART[1]_MOD)
UART1 Secondary Dongle and Status
(UART[1]_DONG)
UART1 Interface Configuration (UART[1]_CONF)
UART1 Reserved MSR (UART[1]_RSVD_MSR) -
Reads return 0; writes have no effect.
UART2 Primary Dongle and Modem Interface
(UART[2]_MOD)
UART2 Secondary Dongle and Status
(UART[2]_DONG)
UART2 Interface Configuration (UART[2]_CONF)
UART2 Reserved MSR (UART[2]_RSVD_MSR) -
Reads return 0; writes have no effect.
Register Name
Receive Data Port (RXD)
Transmit Data Port (TXD)
Interrupt Enable Register (IER)
Event Identification Register (EIR)
FIFO Control Register (FCR)
Link Control Register (LCR)
Bank Select Register (BSR)
Modem/Mode Control Register (MCR)
Link Status Register (LSR)
as 8 bits. The UART/IR Controller treats writes to the upper
56 bits (i.e., bits [63:8]) of the 64-bit MSRs as don’t cares
and always returns 0 on these bits.
The UART/IR Controller Native register set consists of
eight register banks, each containing eight registers, to
control UART operation. All registers use the same 8-byte
address space to indicate I/O Offsets 00h-07h. The Native
registers are accessed via Banks 0 through 7 as I/O Off-
sets. See MSR_LEG_IO (MSR 51400014h) bits [22:20]
and bits [18:16] for setting base address. Each bank and its
offsets are summarized in Table 6-29.
The register summary tables include reset values and page
references where the bit descriptions are provided.
Non-Extended Mode:
Extended Mode: 22h
Reset Value
Reset Value
31506B
0xh
42h
00h
0xh
42h
00h
00h
01h
00h
00h
00h
00h
60h
xxh
xxh
xxh
xxh
Reference
Reference
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