CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 232

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.2.1.4
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.8.4 "MSR Address 3: Error Control" on page 78
for further details.)
232
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:23
Bit
Bit
22
21
20
19
18
17
3
2
1
0
GLD Error MSR (GLPCI_GLD_MSR_ERROR)
Name
EXCEP_ASMI_
EN
SSMI_EN
TAR_ASMI_EN
MAR_ASMI_EN
Name
RSVD
TAS_ERR_
FLAG
PARE_ERR_
FLAG
SYSE_ERR_
FLAG
EXCEP_ERR_
FLAG
RSVD
TAR_ERR_
FLAG
RSVD
51000003h
R/W
00000000_00000000h
31506B
GLPCI_GLD_MSR_SMI Bit Descriptions (Continued)
Description
Exception Bit Enable. Write 1 to enable EXCEP_ASMI_FLAG (bit 19) and to allow the
event.
SSMI Enable. Write 1 to enable SSMI_ASMI_FLAG bit (bit 18) and to allow the event.
Target Abort Received ASMI Enable. Write 1 to enable TAR_ASMI_FLAG (bit 17) and
to allow the event to generate an ASMI.
Master Abort Received ASMI Enable. Write 1 to enable MAR_ASMI_FLAG (bit 16) and
to allow the event to generate an ASMI.
Description
Reserved (Read Only). Returns 0.
Target Abort Signaled Error Flag. If high, records that an ERR was generated due to
signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAS_ERR_EN (bit 6) must be set to enable this event and set flag.
Parity Error Flag. If high, records that an ERR was generated due to the detection of a
PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5) must
be set to enable this event and set flag.
System Error Flag. If high, records that an ERR was generated due to the detection of a
PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN (bit 4)
must be set to enable this event and set flag.
Exception Bit Error Flag. If high, records that the EXCP bit in the received GLIU read or
write response packet is set. Write 1 to clear. EXCEP_ERR_EN (bit 3) must be set to
enable this event and set flag.
Reserved (Read Only). Returns 0.
Target Abort Received Error Flag. If high, records that an ERR was generated due to
the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAR_ERR_EN (bit 1) must be set to enable this event and set flag.
GLPCI_GLD_MSR_ERROR Bit Descriptions
GLPCI_GLD_MSR_ERROR Register Map
RSVD
GeodeLink™ PCI South Bridge Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
RSVD
9
8
7
6
5
4
3
2
1
0