CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 191

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor
5.19
The GeodeLink™ Control Processor (GLCP) functionality
is illustrated in Figure 5-62 and is summarized as:
• Serial to GeodeLink conversion to facilitate JTAG
• Power management support (reset and clock control)
• MSRs
Together with a JTAG controller, the GLCP provides com-
plete visibility of the register state that the chip is in. All reg-
isters are accessible via the JTAG interface.
How the JTAG controller interfaces with the GLCP is
beyond the scope of this document and is not explained
here.
The GLCP also works with the CCU (Clock Control Unit)
blocks of other GeodeLink Devices to provide clock control
via its relevant MSRs. The GLCP supplies the clock enable
signals to all the
power management logic generates a Sleep request or if a
debug event triggers a clock disable situation.
AMD Geode™ CS5535 Companion Device Data Book
accesses to GeodeLink Devices
Req
Out
TAP Controller
Figure 5-62. GLCP Block Diagram
Serial to GL
GeodeLink™ Control Processor
Conversion
Req
In
CCUs,
GeodeLink™ Interface
allowing clocks to be shut off if the
MSR Registers
PCI Interface
Management
PCI Clock
Support
Power
Data Data
Out
In
5.19.1
The main power management functions are performed by
the Power Management Logic, with the GLCP playing a
supporting role. (See Section 5.17 "Power Management
Control" on page 172 for a complete understanding of
power management.)
5.19.1.1 Soft Reset
This is one of the active high soft reset sources going to the
Power
GLCP_SYS_RST register. When active, all circuitry in the
Geode CS5535 companion device is reset (including the
GLCP_SYS_RST register itself).
5.19.1.2 Clock Control
The GLCP provides a mechanism to shut off clocks. The
busy signal from a module can control the clock gating in
its CCU, however, clocks can also be enabled or disabled
by the functional clock enable signals coming from the
GLCP. These enable signals are asynchronous to the
modules and need to be synchronized in the CCU blocks
before being used to enable or disable the functional
clocks.
The clocks can be disabled in one or a combination of the
three ways below. All the MSRs mentioned can be found in
Section 6.18 "Power Management Controller Register
Descriptions" on page 494 and Section 6.20 "GeodeLink™
Control Processor Register Descriptions" on page 531.
1)
The power management circuitry disables the clocks
when going into Sleep. The Sleep sequence is started
by the assertion of Sleep Request from the Power
Management Logic. The GLCP asserts Sleep Request
and waits for the assertion of Sleep Acknowledge,
which indicates that the clocks should be disabled.
There are two ways to do this:
A) If Sleep Acknowledge is asserted and the clock dis-
able delay period has expired, disable the clocks spec-
ified in GLCP_PMCLKDISABLE (MSR 51700009h).
Each bit in GLCP_PMCLKDISABLE corresponds to a
CCU, and when set, indicates that the clock going to
that CCU should be disabled during a Sleep
sequence. The clock disable delay period is specified
by the CLK_DELAY bits in GLCP_CLK_DIS_DELAY
(MSR
CLK_DLY_EN
5170000Bh). It is clocked by the PCI functional clock.
Management
GeodeLink™ Power Management
Support
51700008h),
bit
Logic.
31506B
in
and
GLCP_GLB_PM
is
It
enabled
resides
by
in
(MSR
191
the
the