CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 356

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.9.2
There are two separate PIC sub-blocks in the Geode
CS5535 companion device, connected in a cascaded
arrangement, as is required for a PC-compatible system.
Each PIC has its own native register set, apart from the
MSR registers (unique to the Geode CS5535 companion
device architecture), which are common.
The master PIC occupies I/O Addresses 020h and 021h,
and manages IRQ signals IRQ0 through IRQ7, with IRQ2
claimed as the cascade input for the slave PIC. The slave
PIC occupies I/O Addresses 0A0h and 0A1h, and man-
ages IRQ signals IRQ8 through IRQ15. In this description,
the two addresses of a PIC are called the Even address
(A[0] = 0) and the Odd address (A[0] = 1).
The PIC register set addressing is often confusing due to
some very severe constraints the PIC had in its earliest his-
tory. When it was a separate chip, the package pinout lim-
ited it to only one address line. To make up for this, two bits
of the data written (bits 3 and 4) sometimes serve an
addressing function to select registers.
The chip functions in two fundamental modes with respect
to register accesses: it is either in Operation mode (normal
operation), or it is in Initialization mode (being initialized).
Different sets of registers are selected in each mode.
Operation Mode
When the PIC is in Operation mode, a set of registers may
be accessed, called the Operation Command Words
(OCWs).
• OCW1: The Interrupt Mask register (IMR), may be read
• OCW2: A write-only register that is given commands
• OCW3: A write-only register that is given a different set
Initialization Mode
The PIC is placed into its Initialization mode by a write of a
reserved value (xxx1xxxx) to the even-numbered address
(master 0020h / slave 00A0h). This is the first of a
sequence of writes to a special set of Initialization Control
Word registers (ICW1, ICW2, ICW3 and ICW4) that hold
permanent settings and are normally touched only while
the operating system is booting.
356
or written at any time except during Initialization.
from software. For example, the End of Interrupt
command is written here at the end of interrupt service
to terminate the blocking of interrupts on the basis of
priority.
of commands from software. For example, it is through
this register that software can request images of two
internal registers:
— IRR: Interrupt Request Register -- shows those IRQs
— ISR: In-Service Register -- shows those IRQs that
with pending interrupts that have not yet received an
Interrupt Acknowledge from the CPU.
have received Interrupt Acknowledge, but whose
interrupt service routines have not yet completed.
PIC Native Registers
31506B
6.9.2.1
Writing to the Even Address
Other write and read accesses do not depend directly on
this form of addressing.
Writing to the Odd Address
• Operation Mode: Writes to the Interrupt Mask Register:
• Initialization Mode: Three successive writes to this
Reading from the Even Address
(Operation mode only: the Initialization mode does not
involve reading.)
Reads from this address are generally for special or diag-
nostic purposes. The read must be preceded by writing a
command to OCW3 (above), to select an internal register
to read. This will be the IRR or ISR.
(Another register, “POLL”, historically part of the PIC archi-
tecture, is not provided in the Geode CS5535 companion
device.)
Following that command, the read here will return the
requested value.
Reading from the Odd Address
(Operation mode only: the Initialization mode does not
involve reading.)
Always reads from the Interrupt Mask Register: OCW1.
Associated External Registers
Two directly addressable read/write registers, outside the
addresses of the PICs themselves, have been added to
allow individual control of which IRQs are level sensitive vs.
edge sensitive.
• INT_SEL1, I/O Address 04D0h, controls IRQ1, IRQ3-7
• INT_SEL2, I/O Address 04D1h, controls IRQ8-15
OCW1.
address must immediately follow the write to ICW1
(above), before any other accesses are performed to the
PIC. These writes load ICW2, ICW3 and ICW4 in
succession, after which the PIC automatically transitions
to Operation mode.
4
0
0
1
Data Bit
Programmable Interrupt Controller Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
0 or 1
Register Addressing Scheme
3
0
1
Access Performed
In Operation mode, writes to OCW2, assert-
ing a routine command.
In Operation mode, writes to OCW3, assert-
ing a special or diagnostic command.
Commands written to OCW3 may request to
examine an internal PIC register; if so, this
(even) address must be immediately read to
retrieve the requested value and terminate the
command. See "Reading from the Even
Address" below.
Triggers Initialization mode and writes to
ICW1. Bit 3 is used as a data bit in this case.