CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 400

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.12.5
The bit formats for the registers in Bank 2 are summarized in Table 6-39. Detailed descriptions of each register follow.
6.12.5.1 Baud Generator Divisor Port
Baud Generator Divisor Low Byte (BGD_L)
I/O Offset
Type
Reset Value
Baud Generator Divisor High Byte (BGD_H)
I/O Offset
Type
Reset Value
This port performs the same function as the Legacy Baud Divisor port in Bank 1 and is accessed identically, but does not
change the operation mode of the functional block when accessed. See Section 6.12.4.1 "Legacy Baud Generator Divisor
Port" on page 398 for more details.
Use this port to set the baud when operating in extended mode to avoid fallback to a non-extended operation mode (i.e.,
16550 compatible). When programming the baud, writing to BGD_H causes the baud to change immediately.
6.12.5.2 Extended Control Register 1 (EXCR1)
I/O Offset
Type
Reset Value
Use this register to control operation in the extended mode. Upon reset, all bits are set to 0.
400
Offset
00h
01h
02h
03h
04h
05h
06h
07h
I/O
Bit
7:6
5
7
Register
Bank 2 Register Descriptions
BGD_L
BGD_H
EXCR1
BSR
EXCR2
RSVD
TXFLV
RXFLV
Name
RSVD
EDTLBK
RSVD
Name
00h
R/W
xxh
01h
R/W
xxh
02h
R/W
00h
6
31506B
BKSE
LOCK
7
Description
Reserved. Write as 0.
Enable Transmitter During Loopback. When this bit is set to 1, the transmitter serial
output is enabled and functions normally when loopback is enabled.
EDTLBK
RSVD
RSVD
RSVD
5
RSVD
6
Table 6-39. Bank 2 Bit Map
EXCR1 Bit Descriptions
EXCR1 Register Map
LOOP
EDTLBK
4
5
PRESL[1:0]
DMASWP
LOOP
4
3
BGD[15:8]
BGD[7:0]
RSVD
Bits
AMD Geode™ CS5535 Companion Device Data Book
DMASWP
BSR[6:0]
3
RF_SIZ[1:0]
DMATH
RFL[5:0]
TFL[5:0]
2
UART and IR Port Register Descriptions
DMATH
2
DMANF
1
DMANF
1
TF_SIZ1[1:0]
EXT_SL
EXT_SL
0
0