CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 251

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
6.3.1.5
MSR Address
Type
Reset Value
6.3.1.6
MSR Address
Type
Reset Value
This register is reserved for internal use by AMD and should not be written to.
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:33
63:62
61:32
31:1
31:4
Bit
Bit
3:2
1:0
32
0
GLD Power Management MSR (ACC_GLD_MSR_PM)
GLD Diagnostic MSR (ACC_GLD_MSR_DIAG)
Name
RSVD
UNEXP_TYPE_
ERR_FLAG
RSVD
UNEXP_TYPE_
ERR_EN
Name
RSVD
RSVD
RSVD
PMODE1
PMODE0
51500004h
R/W
00000000_00000000h
51500005h
R/W
00000000_00000000h
Description
Reserved. Reads return 0.
Unexpected Type Error Flag. If high, records that an ERR was generated due to
either an unexpected type event or a master response packet with the EXCEP bit set
has been received. Write 1 to clear; writing 0 has no effect. UNEXP_TYPE_ERR_EN
(bit 1) must be set to enable this event and set flag.
Reserved. Reads return 0.
Unexpected Type Error Enable. Write 1 to enable UNEXP_TYPE_ERR_FLAG (bit
32) and to allow the event to generate an ERR.
Description
Reserved. Reads return value written.
Reserved. Reads return 0.
Reserved. Reads return 0.
Power Mode 1. Power mode for LBus clock.
00: Disable clock gating. Clocks are always on.
01: Enable active hardware clock gating. Clock goes off whenever the LBus circuits
10: Reserved. 11: Reserved.
Power Mode 0. Power mode for GLIU clock
00: Disable clock gating. Clocks are always on.
01: Enable active hardware clock gating. Clock goes off whenever the GLIU circuits
10: Reserved. 11: Reserved.
ACC_GLD_MSR_ERROR Bit Descriptions
are not busy.
are not busy.
ACC_GLD_MSR_PM Bit Descriptions
ACC_GLD_MSR_PM Register Map
RSVD
RSVD
9
8
31506B
7
6
5
4
MODE1
3
P
2
MODE0
1
P
251
0