CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 513

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Power Management Controller Register Descriptions
6.18.3.12 PM De-assert Reset Delay from Standby (PM_RD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
6.18.3.13 PM Working Auxiliary Assert Delay from Standby Wakeup (PM_WKXA)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
19:0
Bit
31
30
Name
RESET_LOCK
RESET_EN
RSVD
RESET_DELAY
38h
R/W
40000100h
3Ch
R/W
00000000h
RSVD
RSVD
Description
Reset Lock. After this bit is set, the value of PM_RD can not be changed until
RESET_STAND# is applied.
Reset Delay Enable. Must be high for the RESET_OUT# output de-assert delay spec-
ified in bits [19:0] (RESET_DELAY) to be applied. (Default = 1.)
Reserved. By convention write 0, but may write anything. Reads return 0.
Reset De-assert Delay. Indicates the number of 32 kHz clock edges to continue
asserting RESET_OUT# from Standby Wakeup. Default value is 8 ms. This delay starts
only if the RESET_WORK# input is de-asserted and the internal Low Voltage Detect
circuit detects normal operating voltages on V
4.6 "Reset Considerations" on page 65 for further details regarding reset conditions.)
Bit 30 (RESET_EN) must be high to enable this delay.
Reset will be applied to the system for the longer of this value or until the internal Low
Voltage Detect circuit detects normal operating voltages on V
PM_WKXA Register Map
PM_RD Bit Descriptions
PM_RD Register Map
WORK_AUX_DELAY
RESET_DELAY
CORE
. (Default = 00100h.) (See Section
9
9
8
8
31506B
7
7
CORE
6
6
5
5
4
4
3
3
2
2
1
1
513
0
0