CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 253

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
6.3.2.2
ACC I/O Offset
Type
Reset Value
6.3.2.3
ACC I/O Offset
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:20
31:24
19:0
Bit
Bit
23
22
Codec GPIO Control Register (ACC_GPIO_CNTL)
Codec Status Register (ACC_CODEC_STATUS)
STS_ADD
Name
RSVD
PIN_DATA
Name
STS_ADD
PRM_RDY_STS
SEC_RDY_STS
04h
R/W
00000000h
08h
R/W
00000000h
RSVD
Description
Reserved. Reads return 0.
Codec GPIO Pin Data. This is the GPIO pin data that is sent to the codec in slot 12 of
the serial output stream.
Note:
Description
Codec Status Address (Read Only). Address of the register for which status is being
returned. This address comes from slot 1 bits [19:12] of the serial input stream.
Note:
Primary Codec Ready (Read Only). Indicates the ready status of the primary codec
(slot 0, bit 15). Software should not access the codec or enable any bus masters until
this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec
Control register (ACC I/O Offset 0Ch[18]).
Secondary Codec Ready (Read Only). Indicates the ready status of the secondary
codec (slot 0, bit 15). Software should not access the codec or enable any bus masters
until this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec
Control register (ACC I/O Offset 0Ch[18]).
ACC_CODEC_STATUS Bit Descriptions
ACC_CODEC_STATUS Register Map
ACC_GPIO_CNTL Bit Descriptions
though some are reserved per the AC97 spec and should be set to zero.
Bit 19 of slot 1 is reserved, but still observable by software.
ACC_GPIO_CNTL Register Map
All 20 bits of the output slot 12 are controllable through this register, even
PIN_DATA
9
9
STS_DATA
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
253
0
0