CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 236

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

236
19:18
12:11
Bit
17
16
15
14
13
10
Name
FPIDE
PPIDE
LRH
RDHP
RSIDE
RPIDE
LEGACT
SDOFF
31506B
IB/OB
OB
IB
IB
IB
IB
IB
IB
IB
Description
Prefetch Primary IDE. If these bits are set, I/O reads to address 1F0h conform to a
prefetching behavior. Under this mode, the GLPCI_SB issues GLIU Read Request
Packets for this specific address before receiving a request on the PCI bus for it. When
IDE prefetch is enabled, all PCI accesses to 1F0h must be DWORDs; that is, 4 bytes.
This setting can only be changed between PIO operations.
00: Off. (Default)
01: At “beginning” initialize pipeline with two read requests.
10: At “beginning” initialize pipeline with three read requests.
11: Reserved.
The prefetch only applies if the current command is "read". The current command is
assumed from the last write to IDE Command Register at 1F7h. The following com-
mands are considered "reads":
Read sectors - 20h
Read multiple - C4h
Read buffer - E4h
Prefetch does not cross sector boundaries; that is, 512-byte boundaries. Any prefetched
data is discarded and the “boundary” set to 0 on any write to 1F7h.
Post Primary IDE. Defaults to 0. If this bit is set, I/O writes to address 1F0h are posted;
that is, the “send response” flag is not set in the GLIU Write Request Packet. Effectively,
an I/O write to this specific address is posted just like memory writes are posted. When
IDE posting is enabled, single and double WORD writes may be mixed without restric-
tion.
Legacy I/O Retry/Hold.
0: Legacy I/O retry.
1: Legacy I/O hold.
Regardless of the above settings an I/O read or write to 1F0h always causes a retry if
data can not be immediately transferred.
Reject DMA High Page. Controls the decoding of I/O range associated with the DMA
High Page registers (480h-48Fh).
0: Considered part of legacy I/O.
1: Subtractive decode.
Reject Secondary IDE. Controls the decoding of I/O range associated with Secondary
IDE address of 170h-177h and 376h.
0: Considered part of legacy I/O.
1: Subtractive decode.
Reject Primary IDE. Controls the decoding of I/O range associated with Primary IDE
address of 1F0h-1F7h and 3F6h.
0: Considered part of legacy I/O.
1: Subtractive decode.
Legacy I/O Space Active Decode.
00: Subtractive decode (claim on fourth clock).
01: Slow decode (claim on third clock).
10: Medium decode (Claim on second clock).
11: Reserved (implemented as medium decode and returned 10 when read).
Non Legacy Subtractive Decode Off.
0: Subtractive decode enabled.
1: Subtractive decode disabled.
GLPCI_CTRL Bit Descriptions (Continued)
GeodeLink™ PCI South Bridge Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book