CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 382
CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
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6.12.1.3 UART[x] Interface Configuration (UART[x]_CONF)
UART1 Interface Configuration (UART[1]_CONF)
MSR Address
Type
Reset Value
UART[x]_CONF derives the control signals for mode and reset control.
382
Bit
RSVD
7
6
5
4
3
2
1
0
7
Name
RSVD
BUSY (RO)
RESET2SIR
EN_BANKS
TEST
PWDN
DEVEN
MSR_SOFT_
RESET
5140003Ah
R/W
42h
BUSY
6
31506B
Description
Reserved. Write as 0.
Busy (Read Only). When high, this bit indicates that the UART busy signal is active.
IR Transmitter and Receiver Reset. Set to 1 to enable reset to the IR transmitter and
receiver. (Default = 0.) Write 0 to bring it out of reset.
Banks Enable. When set to 1, enables access to upper banks (i.e., Banks 2 through 7).
(Default = 0; that is, the UART boots in basic mode [16550 mode where access to upper
banks is not needed]).
Test. When set to 1, the UART goes into test mode and generates a baud clock on the
serial output pin UART[x]_TX (Default = 0.)
Power-down. When set to 1, the UART clocks (24 MHz clock) are frozen, but interrupt
remains enabled. (Default = 0.)
Device Enable. Set to 1 to enable the UART. Resetting this bit disables UART functional-
ity and masks the interrupt. (Default = 1.)
MSR Software Reset. Writing a 1 resets the UART. (Default = 0.)
RESET2SIR
5
UART[x]_CONF Bit Descriptions
UART[x]_CONF Register Map
EN_ BANKS
4
UART2 Interface Configuration (UART[2]_CONF)
MSR Address
Type
Reset Value
TEST
3
AMD Geode™ CS5535 Companion Device Data Book
PWDN
5140003Eh
R/W
42h
2
UART and IR Port Register Descriptions
DEVEN
1
MSR_SOFT_
RESET
0
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