CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 257

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
6.3.2.6
ACC I/O Offset
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:1
Bit
Bit
4
3
2
1
0
0
Bus Master Engine Control Register (ACC_ENGINE_CNTL)
Name
BM2_IRQ_STS
BM1_IRQ_STS
BM0_IRQ_STS
WU_IRQ_STS
IRQ_STS
Name
RSVD
SSND_MODE
14h
R/W
00000000h
ACC_IRQ_STATUS Bit Descriptions (Continued)
Description
Audio Bus Master 2 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 2. Reading the Bus Master 2 IRQ Status
Register clears this bit.
Audio Bus Master 1 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 1. Reading the Bus Master 1 IRQ Status
Register clears this bit.
Audio Bus Master 0 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 0. Reading the Bus Master 0 IRQ Status
Register clears this bit.
Codec GPIO Wakeup IRQ Status. If this bit is set, it indicates that an IRQ was caused
by a GPIO Wakeup Interrupt event (serial data in going high during power-down).
Reading the Codec GPIO Status Register clears this bit.
Codec GPIO IRQ Status. If this bit is set, it indicates that an IRQ was caused by a
GPIO event in the AC97 Codec (slot 12, bit 0). Reading the Codec GPIO Status Regis-
ter clears this bit.
Description
Reserved. Reads return 0.
Surround Sound (5.1) Synchronization Mode. Enables synchronization of Bus Mas-
ters 0, 4, 6, and 7. This bit should be set whenever playing back multi-channel surround
sound. It ensures that the four bus masters stay synchronized and do not introduce any
temporal skew between the separate channels.
ACC_ENGINE_CNTL Bit Descriptions
ACC_ENGINE_CNTL Register Map
RSVD
9
8
31506B
7
6
5
4
3
2
1
257
0