CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 228

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.2
The GeodeLink™ PCI South Bridge (GLPCI_SB) register
set consists of:
• Standard GeodeLink Device (GLD) MSRs
• GLPCI_SB Specific MSRs
• PCI Configuration Registers
The MSRs (both Standard and GLPCI_SB Specific) are
accessed via the RDMSR and WRMSR processor instruc-
tions. The MSR address is derived from the perspective of
the CPU Core. See Section 4.2 "MSR Addressing" on page
59 for more details on MSR addressing.
Additionally, all GLPCI_SB Specific MSRs can be
accessed through both the PCI and GLIU interfaces. See
228
MSR Address
MSR Address
5100002Ch
5100002Ah
5100002Bh
51000000h
51000001h
51000002h
51000003h
51000004h
51000005h
51000010h
51000020h
51000021h
51000022h
51000023h
51000024h
51000025h
51000026h
51000027h
51000028h
51000029h
GeodeLink™ PCI South Bridge Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
31506B
Table 6-5. Standard GeodeLink™ Device MSRs Summary
Register
GLD Capabilities MSR
(GLPCI_GLD_MSR_CAP)
GLD Master Configuration MSR
(GLPCI_GLD_MSR_CONFIG)
GLD SMI MSR (GLPCI_GLD_MSR_SMI)
GLD Error MSR (GLPCI_GLD_MSR_ERROR)
GLD Power Management MSR
(GLPCI_GLD_MSR_PM)
GLD Diagnostic MSR
(GLPCI_GLD_MSR_DIAG)
Register
Global Control (GLPCI_CTRL)
Region 0 Configuration (GLPCI_R0)
Region 1 Configuration (GLPCI_R1)
Region 2 Configuration (GLPCI_R2)
Region 3 Configuration (GLPCI_R3)
Region 4 Configuration (GLPCI_R4)
Region 5 Configuration (GLPCI_R5)
Region 6 Configuration (GLPCI_R6)
Region 7 Configuration (GLPCI_R7)
Region 8 Configuration (GLPCI_R8)
Region 9 Configuration (GLPCI_R9)
Region 10 Configuration (GLPCI_R10)
Region 11 Configuration (GLPCI_R11)
Region 12 Configuration (GLPCI_R12)
Table 6-6. GLPCI_SB Specific MSRs Summary
Section 6.2.3 "PCI Configuration Registers" on page 240
for details.
The PCI configuration registers can only be accessed
through the PCI interface and include:
• The first 16 bytes of standard PCI configuration regis-
• MSR access registers:
Tables 6-5 through 6-7 are register summary tables that
include reset values and page references where the bit
descriptions are provided.
ters.
— PMCTRL
— PMADDR
— PMDATA0
— PMDATA1
GeodeLink™ PCI South Bridge Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
00000000_00000000h
44000030_00000003h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_002051xxh
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
Reset Value
Reset Value
Reference
Reference
Page 230
Page 230
Page 231
Page 232
Page 233
Page 234
Page 234
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238
Page 238