CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 133

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

System Management Bus Controller
3)
4)
5)
6)
Master Transmit
After becoming the bus master, the device can start trans-
mitting data on the bus.
To transmit a byte in an interrupt or polling controlled oper-
ation, the software should:
1)
2)
When either SMBST.NEGACK or SMBST.BER is set, an
interrupt is generated. When the slave responds with a
negative acknowledge, SMBST.NEGACK is set and
SMBST.SDAST
SMBCTL1.INTEN is set, an interrupt is issued.
Master Receive
After becoming the bus master, the device can start receiv-
ing data on the bus.
To receive a byte in an interrupt or polling operation, the
software should:
1)
2)
3)
AMD Geode™ CS5535 Companion Device Data Book
If SMBCTL1.STASTRE is set and the transaction was
successfully completed (i.e., both SMBST.BER and
SMBST.NEGACK are cleared), the STASTR bit is set.
In this case, the SMB Controller stalls any further bus
operations (i.e., holds SCL low). If SMBCTL1.INTEN is
set, it also sends an interrupt request to the host.
If the requested direction is transmit and the START
transaction was completed successfully (i.e., neither
SMBST.NEGACK nor SMBST.BER is set, and no
other master has arbitrated the bus), SMBST.SDAST
is set to indicate that the SMB Controller awaits atten-
tion.
If the requested direction is receive, the START trans-
action
SMBCTL1.STASTRE is cleared, the SMB Controller
starts receiving the first byte automatically.
Check that both SMBST.BER and SMBST.NEGACK
are cleared. If SMBCTL1.INTEN is set, an interrupt is
generated
SMBST.NEGACK is set.
Check that both SMBST.BER and SMBST.NEGACK
are cleared, and that SMBST.SDAST is set. If
SMBCTL1.STASTRE is set, also check that the
SMBST.STASTR is cleared (and clear it if required).
Write the data byte to be transmitted to SMBSDA.
Check
SMBST.BER is cleared. If SMBCTL1.STASTRE is set,
also check that SMBST.STASTR is cleared (and clear
it if required).
Set SMBCTL1.ACK, if the next byte is the last byte
that should be read. This causes a negative acknowl-
edge to be sent.
Read the data byte from SMBSDA.
that
was
remains
when
SMBST.SDAST
completed
cleared.
either
successfully
is
In
SMBST.BER
set
this
and
case,
and
that
or
if
Before receiving the last byte of data, set SMBCTL1.ACK.
Before generating a STOP condition or generating a
repeated START condition, it is necessary to perform an
SDA read and clear the SMBST.SDAST bit.
Master STOP
To end a transaction, set SMBCTL1.STOP before clearing
the current stall flag (i.e., the SDAST, NEGACK, or
STASTR bit of SMBST). This causes the SMB to send a
STOP
SMBCTL1.STOP. A STOP condition may be issued only
when the device is the active bus master (SMBST.MAS-
TER is set).
Master Bus Stall
The SMB Controller can stall the bus between transfers
while waiting for the host response. The bus is stalled by
holding the SCL signal low after the acknowledge cycle.
Note that this is interpreted as the beginning of the follow-
ing bus operation. The user must make sure that the next
operation is prepared before the flag that causes the bus
stall is cleared.
The flags that can cause a bus stall in master mode are:
• Negative acknowledge after sending a byte
• SMBST.SDAST bit is set.
• SMBCTL1.STASTRE = 1, after a successful START
Repeated START
A repeated START is performed when the device is
already the bus master (SMBST.MASTER is set). In this
case, the bus is stalled and the SMB Controller awaits host
handling due to: negative acknowledge (SMBST.NEGACK
= 1), empty buffer (SMBST.SDAST = 1), and/or a stall after
START (SMBST.STASTR = 1).
For a repeated START:
1)
2)
3)
4)
(SMBST.NEGACK = 1).
(SMBST.STASTR = 1).
Set (1) SMBCTL1.START.
In master receive mode, read the last data item from
SMBSDA.
Follow the address send sequence, as described in
“Write the address byte (7-bit target device address)
and the direction bit to SMBSDA. This causes the
SMB Controller to generate a transaction. At the end
of this transaction, the acknowledge bit received is
copied to SMBST.NEGACK. During the transaction,
the SDA and SCL lines are continuously checked for
conflict with other devices. If a conflict is detected, the
transaction is aborted, SMBST.BER is set, and
SMBST.MASTER is cleared.
If the SMB Controller was awaiting handling due to
SMBST.STASTR = 1, clear it only after writing the
requested address and direction to SMBSDA.
condition
immediately,
31506B
and
to
clear
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