CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 555

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
7.3.4
The signals detailed in this sub-section use an “IDE” buffer
type. For a detailed explanation of buffer types, see Table
3-4 "Buffer Type Characteristics" on page 33.
In this subsection, unless otherwise noted:
• All timing specifications are specified under the oper-
Note 1. Per the ATA/ATAPI-5 spec, these signals utilize Output Reference Timing (see Figure 7-3 on page 551) relative to
Note 2. t
Note 3. Per the ATA/ATAPI-5 spec, IDE_DATA write signals utilize Output Reference Timing (see Figure 7-3 on page 551)
Note 4. Per the ATA/ATAPI-5 spec, these signals utilize Input Reference Timing (see Figure 7-4 on page 551) relative to
Note 5. See Figure 7-5 "IDE Data In Timing Non-UltraDMA". As indicated in Note 4, IDE_DATA[15:0] read input is specified
Note 6. For IDE_IRQ0, GPIO2 configured: Aux In and Input Enable = 1; Output Enable, Aux Out 1, and Aux Out 2 = 0.
AMD Geode™ CS5535 Companion Device Data Book
Signal
IDE_CS[1:0]#,
IDE_IOW0,
IDE_AD[2:0],
IDE_RST#,
IDE_DACK0#
IDE_IOR0#
IDE_DATA[15:0] for Write
IDE_DATA[15:0] for Read
IDE_RDY0,
IDE_IRQ0,
IDE_DREQ0#
ating conditions listed in Table 7-3 on page 546 (i.e.,
IDE_IOR0# and IDE_IOW0#. However, the IDE Controller uses the MHZ66_CLK edges to make output changes,
that when taken together, meet all the timing requirements of the referenced spec. Therefore, t
ified and tested relative to the MHZ66_CLK.
t
relative to IDE_IOW0#. However, the IDE Controller uses the MHZ66_CLK edges to make output changes, and
when taken together, meet all the timing requirements of the referenced spec. See Figure 7-5 "IDE Data In Timing
Non-UltraDMA" on page 556.
IDE_IOR0#. However, the IDE Controller samples the inputs with the MHZ66_CLK at the appropriate points in time
to meet all the timing requirements of the referenced spec.
relative to the low-to-high edge of IDE_IOR0#. However, the implementation meets a tighter test spec referenced
to the low-to-high edge of the MHZ66_CLK.
VAL
VAL
IDE Signals in IDE Mode
min times with load of: 15 pF cap to ground.
max times with load of: 40 pF cap to ground.
Table 7-10. IDE Register, PIO, and Multiword DMA Timing Parameters
Parameter
t
t
Async Input
VAL
VAL
Min
NA
3•
2
• Signals are referenced to MHZ66_CLK low-to-high
• Signal and test parameters are defined in Figure 7-2
V
T
edge.
"AC Reference Timing and Test Definition" on page 550.
Max
CORE
CASE
NA
10
13
= All).
and V
Units
ns
ns
ns
CORE_VSB
Comment/Condition
IDE_DACK0# is only used for DMA.
Note 1 and Note 2.
Note 1 and Note 2.
Note 3.
Note 4 and Note 5.
IDE_IRQ0 and IDE_DREQ0# are
only used for DMA.
No clock reference. Note 6.
= All; V
31506B
IO
and V
VAL
IO_VSB
times are spec-
= All;
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