CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 321

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Diverse Integration Logic Register Descriptions
6.6.1.4
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.8.4 "MSR Address 3: Error Control" on page 78
for further on ERR generation details.)
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:55
51:48
Bit
54
53
52
47
GLD Error MSR (DIVIL_GLD_MSR_ERROR)
Name
RSVD
UART1XUART2_
ERR_FLAG
MEM_LBAR_
DECODE_
ERR_FLAG
IO_LBAR_
DECODE_ERR_
FLAG
RSVD
SHTDWN_
ERR_FLAG
RSVD
51400003h
R/W
00000000_00000000h
RSVD
Description
Reserved. Reads return 0. Writes have no effect.
UART1 and UART2 Error Flag. If high, records that an ERR was generated due to a
collision between the two UARTs. UART1 and UART2 are set to the same I/O address
base. No chip selects are asserted and DECODE_ERR_FLAG (bit 33) is asserted.
DECODE_ERR_EN (bit 1) must be high to generate ERR and set flag. Write 1 to clear;
writing 0 has no effect.
Memory LBAR Decode Error Flag. If high, records that an ERR was generated due to
a collision between one memory LBAR and another memory LBAR hit. In this case, NO
chip select is generated and DECODE_ERR_FLAG (bit 33) is asserted.
DECODE_ERR_EN (bit 1) must be high to generate ERR and set flag. Write 1 to clear;
writing 0 has no effect.
I/O LBAR Decode Error Flag. If high, records that an ERR was generated due to a
collision between one I/O LBAR and another I/O LBAR hit. In this case, NO chip select
is generated and DECODE_ERR_FLAG (bit 33) is asserted.DECODE_ERR_EN (bit 1)
must be high to generate ERR and set flag. Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0. Writes have no effect.
Shutdown Error Flag. If high, records that an ERR was generated due to a Shutdown
cycle occurrence. SHTDWN_ERR_EN (bit 15) must be high to generate ERR and set
flag. Write 1 to clear; writing 0 has no effect.
DIVIL_GLD_MSR_ERROR Bit Descriptions
DIVIL_GLD_MSR_ERROR Register Map
RSVD
9
8
31506B
RSVD
RSVD
7
6
5
4
3
2
1
321
0