CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 151

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Low Pin Count Port
5.13.2.1 Host Initiated Cycles
Memory Cycles: Memory read or write cycles are
intended for memory-mapped devices. The ADDR field is a
full 32 bits, and transmitted with most significant nibble
first. Typically a memory device supports much less
addressing and ignores address bits above which it is
capable of decoding.
I/O Cycles: I/O read or write cycles are intended for
peripherals. These cycles are generally used for register or
FIFO accesses and have minimal Sync times. Data trans-
fers are assumed to be exactly 1 byte. The host is respon-
sible for breaking up larger data transfers into 8-bit cycles.
The minimum number of wait states between bytes is 1.
The host initiated cycles are shown in Table 5-24.
5.13.2.2 DMA Initiated Cycles
DMA on LPC is handled through the LDRQ# line from
peripherals and special encoding on LAD[3:0] for the host.
Single, demand, verify, and increment mode are supported
on the LPC interface. Block, decrement, and cascade are
not supported. Channels 0 through 3 are 8-bit channels.
Only 8-bit channels are supported.
Asserting DMA Requests: Peripherals need the DMA
service to encode their request channel number on the
LDRQ# signal. LDRQ# is synchronous with LCLK. Periph-
erals start the sequence by asserting LDRQ# low. The next
3 bits contain the encoded DMA channel number with the
MSB first. And the next bit (ACT) indicates whether the
AMD Geode™ CS5535 Companion Device Data Book
CYCTYP + DIR
Memory or I/O
START
ADDR
SYNC
DATA
TAR
TAR
Table 5-24. Host Initiated Cycles
LDRQ#
LCLK
Read Cycle
Peripheral
Peripheral
Peripheral
Host
Host
Host
Host
Driven By
Figure 5-41. DMA Cycle Timing Diagram
START
Write Cycle
Peripheral
Peripheral
Host
Host
Host
Host
Host
MSB
requested channel is active or not. The case where the
ACT is low (inactive) will be rare, and is only used to indi-
cate that a previous request for that channel is being aban-
doned. After indication, LDRQ# should go high for at least
one clock. After that one clock LDRQ# can be brought low
for next encoding sequence (see Figure 5-41.)
DMA Transfer: Arbitration for DMA channels is performed
through the 8237 within the host. Once the host won the
arbitration, it asserts LFRAME# on the LPC bus. The host
starts a transfer by asserting 0000b on LAD[3:0] with
LFRAME# asserted. The host’s assert “cycle type” and
direction is based on the DMA transfer. In the next cycle it
asserts channel number and in the following cycle it indi-
cates the size of the transfer.
DMA Reads: The host drives 8 bits of data and turns the
bus around, then the peripheral acknowledges the data
with a valid SYNC.
DMA Writes: The host turns the bus around and waits for
data, then the peripheral indicates data is ready through
valid SYNC and transfer of the data.
The DMA initiated cycles are shown in Table 5-25.
CHANNEL
CYCTYP
LSB
START
SYNC
DMA
DATA
SIZE
TAR
TAR
Table 5-25. DMA Initiated Cycles
ACT
Read Cycle
Peripheral)
Peripheral
Peripheral
(Host to
Host
Host
Host
Host
Host
Host
31506B
START
Driven By
(Peripheral to
Write Cycle
Peripheral
Peripheral
Peripheral
Host)
Host
Host
Host
Host
Host
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