CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 312

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6
All registers associated with Diverse Integration Logic
(DIVIL) are MSRs:
• Standard GeodeLink Device (GLD) MSRs
• DIVIL Specific MSRs
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
312
51400006h-
51400000h
51400001h
51400002h
51400003h
51400004h
51400005h
51400007h
51400008h
51400009h
5140000Ah
5140000Bh
Address
Address
MSR
MSR
Diverse Integration Logic Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
31506B
Register Name
GLD Capabilities MSR (DIVIL_GLD_MSR_CAP)
GLD Master Configuration MSR
(DIVIL_GLD_MSR_CONFIG)
GLD SMI MSR (DIVIL_GLD_MSR_SMI)
GLD Error MSR (DIVIL_GLD_MSR_ERROR)
GLD Power Management MSR
(DIVIL_GLD_MSR_PM)
GLD Diagnostic MSR (DIVIL_GLD_MSR_DIAG)
DD Reserved MSRs (DD_MSR_RSVD) (Reads
return 1; writes have no effect.)
Register Name
Local BAR - IRQ Mapper (DIVIL_LBAR_IRQ)
I/O Space - Use of this LBAR is optional. IRQ
Mapper is always accessible via MSR space.
Local BAR - KEL from USB Host Controller 1
(DIVIL_LBAR_KEL1)
Memory Space - First of two ways to access KEL.
KEL operation is not dependent on KEL1 or KEL2
access.
Local BAR - KEL from USB Host Controller 2
(DIVIL_LBAR_KEL2)
Memory Space - Second of two ways to access
KEL. KEL operation is not dependent on KEL1 or
KEL2 access.
Local BAR - SMB (DIVIL_LBAR_SMB)
I/O Space - Local Base Address Register for SMB
Controller native registers.
Table 6-17. Standard GeodeLink™ Device MSRs Summary
Table 6-18. DIVIL Specific MSRs Summary
All MSRs are 64 bits, however, some DIVIL MSRs are
called out as 32 bits. The DIVIL (DD) treats writes to the
upper 32 bits (i.e., bits [63:32]) of the 32-bit MSRs as don’t
cares and always returns 0 on these bits.
The Standard GeodeLink Device MSRs are summarized in
Table 6-17 and the DIVIL Specific MSRs are summarized
in Table 6-18. The reference column in the tables point to
the page where the register maps and bit descriptions are
listed. Some notations in the reference column also point to
other chapters. These MSRs are physically located in the
DIVIL, but the descriptions are documented with the asso-
ciated module and are listed here only for completeness.
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions
FFFFFFFF_FFFFFFFFh
00000000_002DF0xxh
00000000_0000F000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
Reset Value
Reset Value
Reference
Reference
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