CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 503

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Power Management Controller Register Descriptions
6.18.2.7 General Purpose Events Enable 0 (PM_GPE0_EN)
ACPI I/O Offset
Type
Reset Value
PM_GPE0_EN is the Enable register for General Purpose Events. Reads always return the value written. By convention,
bits [23:0] are associated with the Working domain while bits [31:24] are associated with the Standby domain. During
Standby, bits [23:0] are unconditionally cleared. PME status can be read via the corresponding FLAG bit in the
PM_GPE0_STS register (ACPI I/O Offset 18h).
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:22
15:7
Bit
31
30
21
20
19
18
17
16
6
5
Name
GPIOM7_PME_
EN
GPIOM6_PME_
EN
RSVD
GPIOM5_PME_
EN
GPIOM4_PME_
EN
GPIOM3_PME_
EN
GPIOM2_PME_
EN
GPIOM1_PME_
EN
GPIOM0_PME_
EN
RSVD
USBC2_PME_EN
USBC1_PME_EN
1Ch
R/W
00000000h
RSVD
Description
GPIO IRQ/PME Mapper Bit 7 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 7 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 6 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 6 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
Reserved. Reads return 0; writes have no effect
GPIO IRQ/PME Mapper Bit 5 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 5 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 4 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 4 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 3 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 3 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 2 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 2 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 1 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 1 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
GPIO IRQ/PME Mapper Bit 0 PME Enable. When set high, this bit enables the gener-
ation of a PME to the system if a PME occurs via bit 0 of the GPIO IRQ/PME mapper.
Write this bit low to disable the generation of a PME from this source.
Reserved. Reads return 0; writes have no effect
USB Controller #2 PME Enable. When set high, this bit enables the generation of a
PME to the system if a PME occurs via USB Controller #2. Write this bit low to disable
the generation of a PME from this source.
USB Controller #1PME Enable. When set high, this bit enables the generation of a
PME to the system if a PME occurs via USB Controller #2. Write this bit low to disable
the generation of a PME from this source.
PM_GPE0_EN Bit Descriptions
PM_GPE0_EN Register Map
RSVD
9
8
31506B
7
6
5
4
3
2
1
503
0