CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 537

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.20.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
MSR Address
Type
Reset Value
This register has bits that, when set, disable clocks.
6.20.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
MSR Address
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:24
63:34
23:0
33:0
Bit
Bit
Name
RSVD
CLK_DELAY
Name
RSVD
CLK_DIS
RSVD
51700008h
R/W
00000000_00000000h
51700009h
R/W
00000000_00000000h
Description
Reserved. Reads as 0
Clock Disable Delay. If enabled in GLCP_GLB_PM (MSR 5170000Bh[1] = 1), this field
indicates the period to wait from the assertion of SUSPA# before gating-off clocks speci-
fied in GLCP_PMCLKDISABLE (MSR 51700009h). If this delay is enabled, it overrides or
disables the function of GLCP_CLK4ACK (MSR 51700013h). If GLCP_GLB_PM enable
bit is not set (MSR 5170000Bh[1] = 0), but this register (GLCP_CLK_DIS_DELAY) is non-
zero, then this register behaves as a timeout for the CLK4ACK behavior. Note that this
number is in terms of PCI clock cycles, divided by 16.
Description
Reserved
Clock Disable. The bits in this field correspond to the Clock Off (CLK_OFF) bits in
GLCP_CLKOFF (MSR 51700010h). If a bit in this field is set, then the corresponding
CLK_OFF bit will be set when the power management circuitry disables clocks when
entering Sleep. For bit-to-clock correspondences and recommended operational settings
see Table 6-73 on page 536.
GLCP_CLK_DIS_DELAY Bit Descriptions
GLCP_PMCLKDISABLE Bit Descriptions
GLCP_CLK_DIS_DELAY Register Map
GLCP_PMCLKDISABLE Register Map
RSVD
RSVD
CLK_DELAY
9
9
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
537
0
0