CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 386

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

IER, Non-Extended Mode: UART, SIR or Sharp-IR (EXCR1.EXT_SL = 0)
Upon reset, the IER supports UART, SIR and Sharp-IR in non-extended modes.
6.12.3.3 Event Identification (EIR)/FIFO Control Registers (FCR)
The Event Identification Register (EIR) is a read-only register and shares the same address as the write-only FIFO Control
Register (FCR).
Event Identification Register (EIR)
I/O Offset
Type
Reset Value
The EIR indicates the interrupt source, and operates in two modes, non-extended mode (EXT_SL of the EXCR1 register =
0), and extended mode (EXT_SL of the EXCR1 register = 1) (Bank 2, I/O Offset 02h[0]). In non-extended mode (default),
this register functions the same as in the 16550 mode.
EIR, Extended Mode (EXCR1.EXT_SL = 1)
In extended mode, each of the previously prioritized and encoded interrupt sources is broken down into individual bits.
Each bit in this register acts as an interrupt pending flag, and is set to 1 when the corresponding event has occurred or is
pending, regardless of the IER register bit setting. When this register is read, the DMA event (bit 4) is cleared if an 8237
type DMA is used. All other bits are cleared when the corresponding interrupts are acknowledged, by reading the relevant
register (e.g., reading the MSR register clears MS_EV).
386
Bit
7:4
3
2
1
0
7
7
Name
RSVD
MS_IE
LS_IE
TXLDL_IE
RXHDL_IE
RSVD
02h
RO
Extended Mode: 22h
Non-Extended Mode: 01h
6
6
31506B
RSVD
TXEMP_EV
Description
Reserved. Write as 0.
Modem Status Interrupt Enable. Setting this bit to 1 enables the interrupts on modem
status events. (EIR bits [3:0] are 0000.)
Link Status Interrupt Enable. Setting this bit to 1 enables interrupts on Link Status
events. (EIR bits [3:0] are 0110)
Transmitter Low Data Level Interrupt Enable. Setting this bit to 1 enables interrupts
on transmitter low data level events. (EIR bits [3:0] are 0010.)
Receiver High Data Level Interrupt Enable. Setting this bit to 1 enables interrupts on
receiver high data level, or RX_FIFO timeout events. (EIR bits [3:0] are 0100 or 1100.)
IER Non-Extended Mode Bit Descriptions
5
5
IER Non-Extended Mode Register Map
EIR Extended Mode Register Map
DMA_EV
4
4
MS_EV
MS_IE
3
3
AMD Geode™ CS5535 Companion Device Data Book
LS_EV/TXHLT_
LS_IE
EV
2
2
UART and IR Port Register Descriptions
TXLDL_EV
TXLDL_IE
1
1
RXHDL_EV
RXHDL_IE
0
0