CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 507

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Power Management Controller Register Descriptions
6.18.3.5 PM Sleep Clock Delay and Enable (PM_SCLK)
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
6.18.3.6 PM Sleep End Delay (PM_SED)
PMS I/O Offset
Type
Reset Value
Reads always return the value written.
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:0
Bit
31
30
Name
RSVD
SLPCLK_EN
SLPCLK_DELAY
10h
R/W
00000000h
14h
R/W
00000000h
Description
Reserved. By convention write 0, but may write anything.
Sleep Clock Delay Enable. Must be high to assert SLP_CLK_EN# and enable its
assert delay specified in bits [29:0] (SLPCLK_DELAY). Use of this control is required
but not sufficient to enter the Standby state.
WARNING: Using this control immediately turns off all system clocks except the 32 kHz
RTC clock.
Sleep Clock Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait
from the assertion of SUSPA# before asserting SLP_CLK_EN#. Bit 30 (SLPCLK_EN)
must be high to enable this delay.
There is NOT a de-assert delay. The wakeup event causes SLP_CLK_EN# to de-
assert combinatorially from the wakeup event. This event is called Sleep wakeup. The
concept of a Sleep wakeup applies even if Sleep Clock is not used.
PM_SCLK Bit Descriptions
PM_SCLK Register Map
PM_SED Register Map
SLPEND_DELAY
SLPCLK_DELAY
9
9
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
507
0
0