CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 372

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

372
Bit
5
4
3
2
1
0
Name
BER (R/W1C)
NEGACK
(R/W1C)
STASTR (R/W1C)
NMATCH
(R/W1C)
MASTER (RO)
XMIT (RO)
31506B
Description
Bus Error (Read/Write 1 to Clear). Writing 0 to BER is ignored.
0: Writing 1 or SMB disabled.
1: Invalid Start or Stop condition detected during data transfer (i.e., Start or Stop condi-
Neg Acknowledge (Read/Write 1 to Clear). Writing 0 to NEGACK is ignored.
0: Writing 1 or SMB disabled.
1: Transmission not acknowledged on the ninth clock. (In this case, SDAST (bit 6) is
Stall After Start (Read/Write 1 to Clear). Writing 0 to STASTR is ignored. When
STASTR is set, it stalls the SMBus by pulling down the SMB_CLK line, and suspends
any further action on the bus (e.g., receive of first byte in master receive mode).
0: Writing 1 or SMB disabled.
1: This bit is not set in the slave mode and is only set in the master transmit mode.
New Match (Read/Write 1 to Clear). Writing 0 to NMATCH is ignored. If INTEN (SMB
I/O Offset 03h[2]) is set, an interrupt is sent when this bit is set.
0: Software writes 1 to this bit.
1: Address byte follows a Start condition or a Repeated Start, causing a match or a
Master (Read Only).
0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop condition.
1: Bus master request succeeded and master mode active.
Transmit (Read Only). Direction bit.
0: Master/slave transmit mode not active.
1: Master/slave transmit mode active.
tion during the transfer of bits [8:2] and acknowledge cycle), or when an arbitration
problem detected. If the SMBus loses an arbitration this bit is set.
not set.)
When set, this bit indicates that the address was sent successfully and the bus is
now stalled. Note that this mode of operation must be enabled with the STASTRE bit
(SMB I/O Offset 03h[7]) in order for this bit to function this way. Also, if enabled with
INTEN (SMB I/O Offset 03h[2]), an interrupt is sent when this bit is set. This bit is
cleared by writing a 1 to it; writing a 0 has no effect.
global-call match.
SMB_STS Bit Descriptions (Continued)
AMD Geode™ CS5535 Companion Device Data Book
System Management Bus Register Descriptions