CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 125

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Keyboard Emulation Logic
5.10.8
The FA20 sequence occurs frequently in DOS applica-
tions. Mostly, the sequence is to set FA20 high; that is, do
not force address bit 20 to a 0. High is the default state of
this signal. To reduce the number of ASMIs caused by the
A20 sequence, KEL generates an ASMI only if the
GateA20 sequence would change the state of A20.
The A20 sequence is initiated with a write of D1h to I/O
Address 064h. On detecting this write, the KEL sets the
A20Sequence bit in HCE_Control (KEL Memory Offset
100h[5]). It captures the data byte in HCE_Input (KEL
Memory Offset 104h[7:0]), but does not set the InputFull bit
in HCE_Status (KEL Memory Offset 10Ch[1]). When
A20Sequence is set, a write of a value to I/O Address 060h
that has bit 1 set to a value different than A20State in
HCE_Control (KEL Memory Offset 100h[8]) causes Input-
Full to be set and causes an ASMI. An ASMI with both
InputFull and A20Sequence set indicates that the applica-
tion is trying to change the setting of FA20 on the keyboard
controller. However, when A20Sequence is set, and a write
of a value to I/O Address 060h that has bit 1 set to the
same value as A20State in HCE_Control is detected, then
no ASMI will occur.
As mentioned above, a write to I/O Address 064h of any
value other than D1h causes A20Sequence to be cleared.
If A20Sequence is active and a value of FFh is written to
I/O Address 064h, A20Sequence is cleared but InputFull is
not set. A write of any value other than D1h or FFh causes
InputFull to be set, which then causes an ASMI. A write of
FFh to I/O Address 064h when A20Sequence is not set
causes InputFull to be set. The current value of the
A20_Mask is maintained in two unconnected places. The
A20State bit in HCE_Control and bit 1 in Port A. The value
of A20State is only changed via a software write to
HCE_Control. It is set to 0 at reset. The value of bit 1 in
Port A changes on any write to Port A. From reset PortA[1]
is 1.
5.10.9
The processor initialization sequence is possible if either of
the following cases is true:
• A write of a value fed to I/O Address 064h indicates
• Port A initialization, INIT will respond to: Write 01h to I/O
5.10.10 Port A
This register is at I/O Address 092h. It can also be used to
change the state of A20 or to cause an INIT. When 8-bit
data that has its bit 0 set to 1 is written, it causes an INIT.
However, if bit 1 of the 8-bit data is set to 1, it causes a
change in the state of A20 (A20 gets asserted). As above,
an ASMI is only generated on an INIT or A20 event. The
INIT operation always forces A20 high. Writes to bits 2 and
AMD Geode™ CS5535 Companion Device Data Book
processor initialization (INIT) or warm reset. This sets
KEL_INIT_ASMI_FLAG if enabled in the DIVIL. All HCE
registers and Port A are not effected.
Address 092h. (Refer to Section 5.10.10 "Port A".)
Theory - Force A20 Low Sequence
Theory - Processor Initialize Sequence
higher are a “don’t care”. Reads to Port A always return
00h or 02h depending on the state of the bit 1 of Port A.
Note that A20 can be changed with Port A or the GateA20
sequence. Another important point is that A20State in
HCE_Control and bit 1 in Port A are independent from
each other. Writing a 1 to Port A bit 1 does not effect the
A20State bit. Changing the state of the A20State bit does
not effect the bit 1 of Port A.
Note that when A20 has a value of 0, it means that the sec-
ond MB wraps to the first MB. However, a value of 1 means
that A20 is not modified.
The following statements summarize the above INIT and
A20 sequences :
INIT will respond to: Write 01h to I/O Address 092h or FEh
to I/O Address 064h.
A20 toggle will respond to: Write 02h to Address 092h or
Write 00h to Address 092h (bit 1 toggles, bit 0 held at 0),
and Write D1h to I/O Address 064h then write a value to
I/O Address 060h that has bit 1 set to a value different than
the A20State in HceControl register. Trapping will insure
the SMI is taken on the instruction boundary.
A Keyboard INIT will not respond to: Write D1h to I/O
Address 064h followed by a write 02h to I/O Address 060h
(set bit 0 to 0).
5.10.11 Keyboard Emulation Logic MSRs
In addition to HCE_Control (KEL Memory Offset 100h),
there is a KEL Extended Control MSR, MSR_KELX_CTL
(MSR 5140001Fh), to provide additional features.
A “snoop” feature is used when an external LPC based
keyboard controller is used (while the KEL is not enabled).
All I/O accesses to I/O Addresses 060h and 064h proceed
to the LPC, but the KEL snoops or watches for the A20 and
INIT
KEL_A20_ASMI_FLAG or KEL_INIT_ASMI_FLAG in the
DIVIL if enabled.
EEs may be routed such that they generate an IRQ or
ASMI. In the case of Emulation IRQ, the clearing is done
by an operation on the appropriate HCE_Control or
HCE_Status registers. Reading the EE routing bit is not
required for emulation processing via IRQ. This bit does
not effect ASMIs associated with A20 and INIT operations.
All ASMI signals are a single clock pulse wide.
SOFEVENT (Start of Frame Event) is established with bits
[3:2] of MSR 5140001Fh. These bits provide alternative
sources for SOFEVENT. The SOFEVENT can be sourced
from USB1, USB2, or the PIT. A 00 value selects the test
mode.
The Port A enable bit is a mask bit for Port A and its default
state is high.
sequences.
If
31506B
these
occur,
KEL
sets
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