CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 186

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Software Operation
The NAND Flash contains a redundant data area contain-
ing ECC fields. While writing to the NAND Flash, the hard-
ware ECC engine calculates ECC parity, if it is enabled
properly. Software can write the ECC parity bits to the ECC
field after writing the data area. When software reads the
data from NAND Flash, the hardware ECC engine calcu-
lates ECC parity. After the data is read from the NAND
Flash, software can compare the ECC parity in the hard-
ware ECC engine and the ECC parity in the ECC field of
the NAND Flash to determine if the data block is correct.
Each data bit has 11 corresponding parity bits, which can
be determined by the bit address. If one data bit is different
from its original value, 11 ECC parity bits are changed from
the original ECC parity bits. Take the ECC parity from the
hardware ECC engine and perform bit-wise exclusive OR
with it and the ECC parity field in NAND Flash. The result
can be as follows.
1)
2)
3)
4)
5.18.2
The NOR Flash Controller supports up to four independent
chip selects that can be used for NOR Flash devices or
General Purpose Chip Selects (GPCS). Up to 28 bits of
address is supported for each chip select, allowing byte-
wide linear arrays up to 256 MB in memory space. Chips
selects may also be located in I/O space, but the usable
address bits are limited by the over all limits of I/O space.
Each chip select is independently programmable:
• Address Setup: Defaults to seven Local bus clocks
• Read/Write Strobe Width: Defaults to seven Local bus
• Address Hold: Defaults to seven Local bus clocks cycles
• Optional Wait State Insertion: Defaults off, driven by an
• Optional Write Protect: Defaults protected
186
clocks
external input (FLASH_IOCHRDY) to be used by
General Purpose devices.
All bits are 0. The data is correct.
Eleven bits are 1. One bit error has been detected.
Use the eleven bits to identify the error bit position.
One bit is 1. One bit in ECC field is corrupt. Data area
should be OK.
Otherwise, two or more data bits are corrupt. Cannot
be corrected.
NOR Flash Controller/General Purpose
Chip Select
31506B
These settings are located in MSR space and on hard
reset default to the settings listed above. Hence, virtually
any NOR device can be used immediately out of reset for
first instruction fetch. After booting, delays can be pro-
grammed as appropriate.
Special considerations must be made for NOR Flash write
operations. Depending on the manufacturer and write
mode, each write can take from a few microseconds to a
few hundred microseconds. Specifically, the software per-
forming the write must observe the following procedure:
1)
2)
3)
The “wait” in step two is implemented using an appropriate
time base reference. There is no reference within the Flash
Controller subsystem.
Some NOR devices provide a ready line that de-asserts
during the “wait” in step two. Direct use of this signal is not
supported by the Flash Controller. The NOR write software
should use an appropriate time base reference to deter-
mine when the device is ready, that is, determine how long
to wait for the current write to complete before starting
another write. Alternatively, the NOR device internal status
may be read to determine when the write operation is com-
plete. Refer to NOR Flash manufactures data sheets for
additional write operation details.
Write to device.
Wait an amount of time dependent on manufacturer’s
specifications.
Repeat from #1 until all writes are completed.
AMD Geode™ CS5535 Companion Device Data Book
Flash Controller