CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 255

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
30:24
23:22
Bit
31
21
20
19
18
17
Name
RW_CMD
CMD_ADD
COMM_SEL
PD_PRIM
PD_SEC
RSVD
LNK_SHTDWN
LNK_WRM_RST
Description
Codec Read/Write Command. This bit specifies a read or write operation targeting the
AC97 codec’s registers.
0: Write.
1: Read.
This bit determines whether slot 1, bit 19 of the serial output stream will be high or low.
Codec Command Address. Address of the codec control register for which the com-
mand is being sent. This address goes in slot 1, bits [18:12] of the serial output stream.
This is used for specifying the address of a register in the AC97 codec (for reading or
writing).
Audio Codec Communication. Selects which codec to communicate with (for register
reads/writes):
00: Codec 1 (Primary)
01: Codec 2 (Secondary)
10: Codec 3
11: Codec 4
These bits determine output slot 0, bits [1:0]. When these bits are non-zero, bits [14:13]
of output slot 0 must be set to zeros regardless of the validity of slot 1 and slot 2.
Power-down Semaphore for Primary Codec. This bit is used by software in conjunc-
tion with bit 20 to coordinate the power-down of the two codecs. This bit is intended to
be set by the audio driver to indicate to the modem driver that the audio codec has
been prepared for power-down. Internally it does not control anything, and is simply a
memory bit.
Power-down Semaphore for Secondary Codec. This bit is used by software in con-
junction with bit 21 to coordinate the power-down of the two codecs. This bit is intended
to be set by the modem driver to indicate to the audio driver that the modem codec has
been prepared for power-down. Internally it does not control anything, and is simply a
memory bit.
Reserved. Reads return 0.
AC Link Shutdown. Informs the Controller that the AC Link is being shutdown.
This bit should be set at the same time that the codec power-down command is issued
to the codec.
Setting this bit also clears both Codec Ready bits in the Codec Status register (ACC I/O
Offset 08h[23:22]).
Issuing a warm reset via bit 17 clears this bit.
If the codec has been powered off and back on, a warm reset is unnecessary, this bit
should be cleared manually.
AC Link Warm Reset. Setting this bit initiates the AC Link/codec warm reset process.
It is automatically cleared by hardware once the serial bit clock resumes. This should
only be set when the codec(s) are powered down. Once set, software should then wait
for “Codec Ready” before accessing the codec.
ACC_CODEC_CNTL Bit Descriptions
31506B
255