CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 450

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.16
The registers for the General Purpose Input Output (GPIO)
are divided into two sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• GPIO Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
The GPIO Native registers are accessed via a Base
Address Register, MSR_LBAR_GPIO (MSR 5140000Ch),
as I/O Offsets. (See Section 6.6.2.5 on page 328 for bit
descriptions of the Base Address Register.)
The Native registers associated with GPIO configuration
are broadly divided into three categories:
1)
450
GPIO Low Bank Feature Bit Registers
GPIO I/O
(Note 1)
DIVIL, see Section 6.6.1 on page 317.)
Offset
GPIO Low/High Bank Feature Bit Registers.
These registers (summarized in Table 6-57) control
basic GPIO features. The Feature Bit registers use the
atomic programming model except where noted. See
0Ch
1Ch
2Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
GPIO Subsystem Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Table 6-57. GPIO Low/High Bank Feature Bit Registers Summary
31506B
Width
(Bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Register Name
GPIO Low Bank Output Value (GPIOL_OUT_VAL)
GPIO Low Bank Output Enable (GPIOL_OUT_EN)
GPIO Low Bank Output Open-Drain Enable
(GPIOL_OUT_OD_EN)
GPIO Low Bank Output Invert Enable
(GPIOL_OUT_INVRT_EN)
GPIO Low Bank Output Auxiliary 1 Select
(GPIOL_OUT_AUX1_SEL)
GPIO Low Bank Output Auxiliary 2 Select
(GPIOL_OUT_AUX2_SEL)
GPIO Low Bank Pull-Up Enable (GPIOL_PU_EN)
GPIO Low Bank Pull-Down Enable (GPIOL_PD_EN)
GPIO Low Bank Input Enable (GPIOL_IN_EN)
GPIO Low Bank Input Invert Enable
(GPIOL_IN_INVRT_EN)
GPIO Low Bank Input Filter Enable
(GPIOL_IN_FLTR_EN)
GPIO Low Bank Input Event Count Enable
(GPIOL_IN_EVNTCNT_EN)
GPIO Low Bank Read Back (GPIOL_READ_BACK)
GPIO Low Bank Input Auxiliary 1 Select
(GPIOL_IN_AUX1_SEL)
2)
3)
The reference column in the summary tables point to the
page where the detailed register maps and bit descriptions
are listed. The Low Bank refers to GPIO[15:0] while the
Note: All register bits dealing with GPIO31, GPIO30,
High Bank refers to GPIO[31:16] .
Section 6.16.1 "Atomic Bit Programming Model" on
page 454 for details.
Input Conditioning Function Registers.
These registers (summarized in Table 6-58 on page
452) are associated with the eight digital filter/event
counter pairs that can be shared with the 32 GPIOs.
These registers are not based on the atomic bit pro-
gramming model.
GPIO Interrupt and PME Mapper Registers.
These registers (summarized in Table 6-59 on page
453) are used for mapping any GPIO to one of the
eight PIC-level interrupts or to one of the eight PME
(Power Management Event) inputs.
GPIO29 and GPIO23 are reserved.
AMD Geode™ CS5535 Companion Device Data Book
GPIO Subsystem Register Descriptions
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
1000EFFFh
EFFF1000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
FFFF0000h
00000000h
Reset
Value
Reference
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