CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 85

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI South Bridge
5.2.1
The GeodeLink Interface block provides a thin protocol
conversion layer between the transaction forwarding mod-
ule and the GLIU. It is responsible for multiplexing in-bound
write request data with out-bound read response data on
the single GLIU data out bus.
5.2.2
The FIFO block consists of a collection of in-bound and
out-bound FIFOs. Each FIFO provides simple, synchro-
nous interfaces to the reader and to the writer.
The FIFO block also includes synchronization logic for a
few non-FIFO related signals and clock gating logic.
5.2.3
The Transaction Forwarding block receives, processes,
and forwards transaction requests and responses between
the GeodeLink Interface and PCI Bus Interface blocks. It
implements the transaction ordering rules. It performs
write/read prefetching as needed. It also performs the nec-
essary translation between GLIU and PCI commands. The
Transaction Forwarding block also handles the conversion
between 64-bit GLIU data paths and 32-bit PCI data paths.
Out-bound transactions are handled in a strongly ordered
fashion. All out-bound memory writes are posted. The
SEND_RESPONSE flag is never expected to be set in a
memory write and is ignored. Any queued out-bound
requests are flushed prior to handling an in-bound read
request.
All in-bound memory writes are posted. South bridge mas-
ter out-bound read request data can pass in-bound writes.
Thus, a pending out-bound read request need not be
deferred while posted in-bound write data is waiting to be
flushed or is in the process of being flushed. The out-bound
read request may be performed on the PCI bus at the
same time that the in-bound write data is flowing through
the GLIU.
When handling an in-bound read request, the intended size
of the transfer is unknown. In-bound read requests for non-
prefetchable addresses will only fetch the data explicitly
indicated in the PCI transaction. Thus, all in-bound read
requests made to non-prefetchable addresses will return at
most a single 32-bit WORD. In-bound read requests made
to prefetchable memory may cause more than a 32-bit
WORD to be prefetched. The amount of data prefetched is
configurable via the read threshold fields of the Global
Control (GLPCI_CTRL), MSR 51000010h. Multiple read
requests may be generated to satisfy the read threshold
value.
In-bound read requests may pass posted in-bound write
data when there is no address collision between the read
request and the address range of the posted write data (dif-
ferent cache lines) and the read address is marked as
being prefetchable.
AMD Geode™ CS5535 Companion Device Data Book
GeodeLink™ Interface
FIFOs/Synchronization
Transaction Forwarding
Support IDE data port Read Prefetch when MSR Control
register (MSR 51000010h[19:18]) is set to IDE prefetch for
performance enhancement. I/O reads to address 1F0h can
follow a prefetching behavior. When enabled, the
GLPCI_SB issues GLIU Read Request Packets for this
specific address before receiving a request on the PCI bus
for it. All PCI accesses to 1F0h must be DWORDs; that is,
4 bytes.
5.2.4
The PCI Bus Interface block provides a protocol conver-
sion layer between the transaction forwarding module and
the PCI bus. The master and target portions of this module
operate independently. Thus, out-bound write requests and
in-bound read responses are effectively multiplexed onto
the PCI bus. It includes address decoding logic to recog-
nize distinct address regions for slave operation. Each
address region is defined by a starting address, an address
mask, and some attached attributes (i.e., memory and/or
I/O space indicator, prefetchable, retry/hold, postable
memory write, region enable).
The PCIF is responsible for retrying out-bound requests
when a slave termination without data is seen on the PCI
bus. It also must restart transactions on the PCI that are
prematurely ended with a slave termination. This module
also always slave terminates in-bound read transactions
issued to non-prefetchable regions after a single WORD
has been transferred.
5.2.5
The CPU Interface Serial block provides a serial interface
to the CPU for side-band signals. From reset, the
GLPCI_SB connects only the SUSP# signal to the serial
output. All other signals must be added by programming
the CIS mode (MSR 51000010h[4:3]). Any change of the
signals selected from the 16 side-band signals will start
shifting to the CPU all 20 bits of the CIS register including
two START bits (00) and two padding STOP bits (11).
Three different modes control the selection of the side-
band signals to the CIS shift register.
5.2.6
An ID select register, IDSEL[31:0], is used for programma-
ble ID selection. Only one bit in IDSEL[31:12] is set and
used as a chip select (i.e., compared with AD[31:12]) dur-
ing a PCI configuration write/read. The reset value of the
IDSEL register is 02000000h. After reset, the first 32-bit I/O
write PCI command (i.e., BE# = 0h) with address
00000000h and one bit set in AD[31:0] is assumed to ini-
tialize the IDSEL register. Only data with one bit set in
AD[31:0] is considered valid. All other values are ignored
and will not change the contents of IDSEL.
PCI Bus Interface
CPU Interface Serial
Programmable ID Selection
31506B
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