CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 393

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.3.5 Modem/Mode Control Register (MCR)
I/O Offset
Type
Reset Value
MCR controls the virtual interface with the modem or data communications set in loopback mode, and the device opera-
tional mode when the device is in the extended mode. This register function differs for extended and non-extended modes.
Modem control pins are not available and are replaced with the virtual interface (except RTS and DTR signals) controlled
by software only through MSR_UART[x]_MOD (see Section 6.12.1.1 on page 380).
MCR, Extended Mode (EXCR1.EXT_SL = 1)
In extended mode, this register is used to select the operation mode (IrDA, Sharp, etc.) of the device and enable the DMA
interface. In these modes, the interrupt output signal is always enabled, and loopback can be enabled by setting bit 4 of
EXCR1. Bits 2 to 7 should always be initialized when the operation mode is changed from non-extended to extended.
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:5
4
3
2
1
0
7
Name
MDSL[2:0]
RSVD
TX_DFR
DMA_EN
RTS
DTR
MDSL[2:0]
04h
R/W
00h
6
Description
Mode Select [2:0]. These bits select the operation mode of the functional block when in
extended mode. When the mode is changed, the TX_FIFO and RX_FIFOs are flushed,
Link Status and Modem Status Interrupts are cleared, and all of the bits in the Auxiliary
Status and Control register are cleared.
000: UART (Default)
001: Reserved
010: Sharp-IR
011: SIR
100: Reserved
101: Reserved
110: CEIR
111: Reserved
Reserved. Write as 0.
Transmit Deferral. For a detailed description of the transmit deferral see Section 5.12.1.6
"Transmit Deferral" on page 142. This bit is effective only if the TX_FIFO is enabled (FCR
bit 0 = 1).
0: No transmit deferral enabled. (Default.)
1: Transmit deferral enabled.
DMA Enable. When set to1, DMA mode of operation is enabled. When DMA is selected,
transmit and/or receive interrupts should be disabled to avoid spurious interrupts. DMA
cycles always address the Data Holding registers or FIFOs, regardless of the selected
bank.
0: DMA mode disabled. (Default.)
1: DMA mode enabled.
Request To Send. When loopback is enabled (bit 4 of EXCR1 = 1, Bank 2, I/O Offset 02h),
this bit internally drives both CTS and DCD. Otherwise it is unused.
Data Terminal Ready. When loopback is enabled (bit 4 of EXCR1 = 1, Bank 2, I/O Offset
02h), this bit internally drives both DSR and RI. Otherwise it is unused.
5
MCR Extended Mode Bit Descriptions
MCR Extended Mode Register Map
RSVD
4
TX_DFR
3
DMA_EN
2
31506B
RTS
1
DTR
0
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