MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 795

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Applications
9.8.1.1 MC68EC030 READS AND WRITES TO QUICC. The basic connection is made
through the data and address bus. All 32 data lines are routed between devices, which is
required for the connection. In slave mode, the QUICC is not allowed to use its 16-bit data
bus mode.(Assertion of 16BM pin during reset)
Twenty-eight address lines are routed between devices, giving a 256-Mbyte shared address
capability. It is possible to share all 32 address lines between devices, but the QUICC would
then lose its write enable lines (WE3–WE0). Since these lines are very useful in memory
interfaces, they are used in this application.
When running in normal slave mode with an MC68EC030 master, the QUICC provides a
few signal changes to support the MC68EC030. These signal changes allow the QUICC to
monitor and control the system buses in a glueless manner. The changed bus signals are
bus request (BR), bus grant (BG), and bus grant acknowledge (BGACK). When operating
in normal slave mode, the direction of these signals is reversed. Therefore, BR is an output;
BG is an input. In addition, BGACK becomes an I/O signal, rather than just an input.
9.8.1.2 CLOCKING STRATEGY. In this application, a single 25-MHz external oscillator is
used to drive the QUICC and the MC68EC030, which allows the synchronous mode of the
QUICC memory controller to be used. When considering buffering of outputs and board lay-
out, designers need to consider the synchronous timing requirements of the QUICC.
Designers considering the possibility of running asynchronously or with faster MC68EC030
clock speeds should reference paragraph 9.8.5 Using a Higher Speed MC68EC030 Master
with the QUICC.
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MC68360 USER’S MANUAL
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