MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 462

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
struct a data clock that may be used as the SCC receive and/or transmit clock. In all modes,
the DPLL uses the input clock to determine the nominal bit time.
At the beginning of operation, the DPLL is in search mode. In this mode, the first transition
resets the internal DPLL counter and begins DPLL operation. While the counter is counting,
the DPLL watches the incoming data stream for transitions. Whenever a transition is
detected, the DPLL makes a count adjustment to produce an output clock that tracks the
incoming bits.
The DPLL provides a carrier-sense signal. The carrier-sense signal indicates that there are
data transfers on the RXD line. It is asserted as soon as a transition is detected on the RXD
line, and it is negated after a programmable number of clocks have been detected with no
transitions, using the TSNC bits in the GSMR.
To prevent the DPLL from locking on the wrong edges and to provide a fast synchronization,
the DPLL should generally receive a preamble pattern prior to the data. In some protocols,
the preceding flags or syncs are used. However, some protocols require a special pattern,
such as alternating ones and zeros. For the case of transmission, the SCC has an option to
generate preamble patterns as programmed in the TPP and TPL bits of the GSMR.
The DPLL can also be used to invert the data stream on receive or transmit. This feature is
available in all encodings, including the standard NRZ data format.
The DPLL offers a choice on the transmitter during idle of whether to force the TXD line to
a high voltage or to continue encoding the data supplied to it.
The DPLL is used for the UART encoding/decoding. This gives the user the option of select-
ing the divide ratio used in the UART decoding process (8, 16, or 32). Typically, the 16
option is chosen by users.
The maximum data rate that can be supported with the DPLL is 3.125 MHz when working
with a 25-MHz system clock, which assumes the 8 option is chosen: 25 MHz/8 = 3.125
MHz. Thus, the frequency applied to the CLKx pin or generated by an internal baud rate gen-
erator may be up to 25 MHz on a 25-MHz QUICC, if the DPLL 8 , 16 , or 32 options are
used.
7-138
The QUICC receiver require the above preambles.
NOTES:
Differential Manchester.
Decoding Method
NRZI Space
Manchester
NRZI Mark
FM0
FM1
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 7-6. Preamble Requirement
MC68360 USER’S MANUAL
Go to: www.freescale.com
Preamble Pattern
Repeating 10's
All zeros
All zeros
All ones
All ones
All ones
Max Preamble Length Required
8-bits
8-bits
8-bits
8-bits
8-bits
8-bits