MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 228

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
CPU32+
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
PERIOD
PERIOD
(ABSORBED BY
(ABSORBED BY
INSTRUCTION A)
INSTRUCTION B)
Figure 5-32. Attributed Instruction Times
5.7.1.5 EFFECTS OF WAIT STATES. The CPU32+ access time for on-chip peripherals is
two clocks. While two-clock external accesses are possible when the bus is operated in a
synchronous mode, a typical external memory speed is three or more clocks.
All instruction times listed in this section are for word access only (unless an explicit excep-
tion is given), and are based on the assumption that both instruction fetches and operand
cycles are to a two-clock memory. Wait states due to slow external memory must be added
to the access time for each bus cycle.
A typical application has a mixture of bus speeds—program execution from an off-chip
ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and
accesses to external peripherals with speeds ranging from moderate to very slow. To arrive
at an accurate instruction time calculation, each bus access must be individually considered.
Many instructions have a head cycle count, which can overlap the cycles of an operand fetch
to slower memory started by a previous instruction. In these cases, an increase in access
time has no effect on the total execution time of the pair of instructions.
To trace instruction execution time by monitoring the external bus, note that the order of
operand accesses for a particular instruction sequence is always the same provided bus
speed is unchanged and the interleaving of instruction prefetches with operands within each
sequence is identical.
5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time for
an instruction depends on the amount of overlap with previous and subsequent instructions.
To calculate an instruction time estimate, the entire code sequence must be analyzed. To
derive the actual instruction execution times for an instruction sequence, the instruction
times listed in the tables must be adjusted to account for overlap.
The formula for this calculation is as follows:
C
min (T
, H
)
C
min (T
, H
)
C
min (T
, H
)
. .
1
2
2
2
3
3
3
4
1
where:
C
is the number of cycles listed for instruction N
N
5-86
MC68360 USER’S MANUAL
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