MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 435

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Each SCC may be connected to its own set of pins on the QUICC. This configuration is
called the NMSI and is described in 7.8 Serial Interface with Time Slot Assigner. In this con-
figuration, each SCC can support the standard modem interface signals (RTS, CTS, and
CD) through the port C pins and the CPM interrupt controller (CPIC). Additional handshake
signals may be supported with additional parallel I/O lines.
Refer to the SCC block diagram in Figure 7-37.
7.10.2 General SCC Mode Register (GSMR)
Each SCC contains a GSMR that defines all the options that are common to each SCC,
regardless of the protocol. Detailed descriptions of some of the operations of the GSMR are
given in later sections. GSMR is a read-write register that is cleared at reset. Since GSMR
is 64 bits in length, it is accessed as GSMR_L and GSMR_H. GSMR_L contains the first
(low-order) 32 bits of GSMR; GSMR_H contains the last 32 bits of GSMR.
63
47
31
15
—
RXD
TCRC
RDCR
MODEM LINES
62
46
30
14
DECODER
EDGE
REVD
61
45
29
13
PERIPHERAL BUS
IMB
RENC
TRX
TCI
60
44
28
12
RECEIVER
DELIMITER
CONTROL
UNIT
Freescale Semiconductor, Inc.
TTX
59
43
27
11
For More Information On This Product,
TSNC
Figure 7-37. SCC Block Diagram
CDP
58
42
26
10
MC68360 USER’S MANUAL
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RECEIVE
SHIFTER
DATA
FIFO
TENC
CTSP
RINV
57
41
25
9
REGISTERS
CONTROL
TINV
CDS
56
—
40
24
8
TRANSMIT
SHIFTER
DATA
FIFO
CTSS
55
39
23
7
DIAG
TFL
TPL
Serial Communication Controllers (SCCs)
54
38
22
6
TRANSMITTER
CONTROL
DELIMITER
RFW
ENR
UNIT
53
37
21
5
TXSY
ENT
52
36
20
4
INTERNAL CLOCKS
TPP
MODEM LINES
GENERATOR
AND CLOCK
RECOVERY
ENCODER
CLOCK
51
35
19
DPLL
3
SYNL
Tend
50
34
18
2
TXD
MODE
RTSM
49
33
17
1
TDCR
TCLKx
RCLKx
RSYN
GDE
48
32
16
0